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feat(rme): add xlat table library changes for FEAT_RME 

FEAT_RME adds a new bit (NSE) in the translation table descriptor
to determine the Physical Address Space (PAS) of an EL3 stage 1
translation according to the following mapping:

	TTD.NSE    TTD.NS  |  PAS
	=================================
	  0          0	   |  Secure
	  0	     1	   |  Non-secure
	  1	     0	   |  Root
	  1	     1	   |  Realm

This patch adds modifications to version 2 of the translation table
library accordingly. Bits 4 and 5 in mmap attribute are used to
determine the PAS.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I82790f6900b7a1ab9494c732eac7b9808a388103
This commit is contained in:
Zelalem Aweke 2021-07-08 17:23:04 -05:00
parent 4693ff7225
commit 362182386b
8 changed files with 105 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
include/lib/xlat_tables/xlat_tables.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -72,6 +72,13 @@
#define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE)
#define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER)
/* Memory type for EL3 regions */
#if ENABLE_RME
#error FEAT_RME requires version 2 of the Translation Tables Library
#else
#define EL3_PAS MT_SECURE
#endif
/*
* Structure for specifying a single region of memory.
*/

3
include/lib/xlat_tables/xlat_tables_defs.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -142,6 +142,7 @@
#define AP_NO_ACCESS_UNPRIVILEGED (AP1_NO_ACCESS_UNPRIVILEGED << 4)
#define AP_ONE_VA_RANGE_RES1 (AP1_RES1 << 4)
#define NS (U(0x1) << 3)
#define EL3_S1_NSE (U(0x1) << 9)
#define ATTR_NON_CACHEABLE_INDEX ULL(0x2)
#define ATTR_DEVICE_INDEX ULL(0x1)
#define ATTR_IWBWA_OWBWA_NTR_INDEX ULL(0x0)

30
include/lib/xlat_tables/xlat_tables_v2.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -60,17 +60,22 @@
#define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK)
/* Access permissions (RO/RW) */
#define MT_PERM_SHIFT U(3)
/* Security state (SECURE/NS) */
#define MT_SEC_SHIFT U(4)
/* Physical address space (SECURE/NS/Root/Realm) */
#define MT_PAS_SHIFT U(4)
#define MT_PAS_MASK (U(3) << MT_PAS_SHIFT)
#define MT_PAS(_attr) ((_attr) & MT_PAS_MASK)
/* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */
#define MT_EXECUTE_SHIFT U(5)
#define MT_EXECUTE_SHIFT U(6)
/* In the EL1&0 translation regime, User (EL0) or Privileged (EL1). */
#define MT_USER_SHIFT U(6)
#define MT_USER_SHIFT U(7)
/* Shareability attribute for the memory region */
#define MT_SHAREABILITY_SHIFT U(7)
#define MT_SHAREABILITY_SHIFT U(8)
#define MT_SHAREABILITY_MASK (U(3) << MT_SHAREABILITY_SHIFT)
#define MT_SHAREABILITY(_attr) ((_attr) & MT_SHAREABILITY_MASK)
/* All other bits are reserved */
/*
@ -91,8 +96,10 @@
#define MT_RO (U(0) << MT_PERM_SHIFT)
#define MT_RW (U(1) << MT_PERM_SHIFT)
#define MT_SECURE (U(0) << MT_SEC_SHIFT)
#define MT_NS (U(1) << MT_SEC_SHIFT)
#define MT_SECURE (U(0) << MT_PAS_SHIFT)
#define MT_NS (U(1) << MT_PAS_SHIFT)
#define MT_ROOT (U(2) << MT_PAS_SHIFT)
#define MT_REALM (U(3) << MT_PAS_SHIFT)
/*
* Access permissions for instruction execution are only relevant for normal
@ -149,6 +156,13 @@ typedef struct mmap_region {
#define EL3_REGIME 3
#define EL_REGIME_INVALID -1
/* Memory type for EL3 regions. With RME, EL3 is in ROOT PAS */
#if ENABLE_RME
#define EL3_PAS MT_ROOT
#else
#define EL3_PAS MT_SECURE
#endif /* ENABLE_RME */
/*
* Declare the translation context type.
* Its definition is private.

17
lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
View File

@ -39,6 +39,23 @@ size_t xlat_arch_get_max_supported_granule_size(void)
return PAGE_SIZE_4KB;
}
/*
* Determine the physical address space encoded in the 'attr' parameter.
*
* The physical address will fall into one of two spaces; secure or
* nonsecure.
*/
uint32_t xlat_arch_get_pas(uint32_t attr)
{
uint32_t pas = MT_PAS(attr);
if (pas == MT_NS) {
return LOWER_ATTRS(NS);
} else { /* MT_SECURE */
return 0U;
}
}
#if ENABLE_ASSERTIONS
unsigned long long xlat_arch_get_max_supported_pa(void)
{

29
lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -53,6 +53,33 @@ size_t xlat_arch_get_max_supported_granule_size(void)
}
}
/*
* Determine the physical address space encoded in the 'attr' parameter.
*
* The physical address will fall into one of four spaces; secure,
* nonsecure, root, or realm if RME is enabled, or one of two spaces;
* secure and nonsecure otherwise.
*/
uint32_t xlat_arch_get_pas(uint32_t attr)
{
uint32_t pas = MT_PAS(attr);
switch (pas) {
#if ENABLE_RME
/* TTD.NSE = 1 and TTD.NS = 1 for Realm PAS */
case MT_REALM:
return LOWER_ATTRS(EL3_S1_NSE | NS);
/* TTD.NSE = 1 and TTD.NS = 0 for Root PAS */
case MT_ROOT:
return LOWER_ATTRS(EL3_S1_NSE);
#endif
case MT_NS:
return LOWER_ATTRS(NS);
default: /* MT_SECURE */
return 0U;
}
}
unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr)
{
/* Physical address can't exceed 48 bits */

11
lib/xlat_tables_v2/xlat_tables_core.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -125,11 +125,14 @@ uint64_t xlat_desc(const xlat_ctx_t *ctx, uint32_t attr,
* faults aren't managed.
*/
desc |= LOWER_ATTRS(ACCESS_FLAG);
/* Determine the physical address space this region belongs to. */
desc |= xlat_arch_get_pas(attr);
/*
* Deduce other fields of the descriptor based on the MT_NS and MT_RW
* memory region attributes.
* Deduce other fields of the descriptor based on the MT_RW memory
* region attributes.
*/
desc |= ((attr & MT_NS) != 0U) ? LOWER_ATTRS(NS) : 0U;
desc |= ((attr & MT_RW) != 0U) ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO);
/*

5
lib/xlat_tables_v2/xlat_tables_private.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -40,6 +40,9 @@
extern uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
/* Determine the physical address space encoded in the 'attr' parameter. */
uint32_t xlat_arch_get_pas(uint32_t attr);
/*
* Return the execute-never mask that will prevent instruction fetch at the
* given translation regime.

18
lib/xlat_tables_v2/xlat_tables_utils.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -95,7 +95,23 @@ static void xlat_desc_print(const xlat_ctx_t *ctx, uint64_t desc)
? "-USER" : "-PRIV");
}
#if ENABLE_RME
switch (desc & LOWER_ATTRS(EL3_S1_NSE | NS)) {
case 0ULL:
printf("-S");
break;
case LOWER_ATTRS(NS):
printf("-NS");
break;
case LOWER_ATTRS(EL3_S1_NSE):
printf("-RT");
break;
default: /* LOWER_ATTRS(EL3_S1_NSE | NS) */
printf("-RL");
}
#else
printf(((LOWER_ATTRS(NS) & desc) != 0ULL) ? "-NS" : "-S");
#endif
#ifdef __aarch64__
/* Check Guarded Page bit */