Merge pull request #1170 from dp-arm/dp/amu
Add support for Activity Monitors
This commit is contained in:
davidcunado-arm
GitHub
commit
3642ca951b
2
Makefile
2
Makefile
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@ -456,6 +456,7 @@ $(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS))
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$(eval $(call assert_boolean,CTX_INCLUDE_FPREGS))
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$(eval $(call assert_boolean,DEBUG))
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$(eval $(call assert_boolean,DISABLE_PEDANTIC))
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$(eval $(call assert_boolean,ENABLE_AMU))
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$(eval $(call assert_boolean,ENABLE_ASSERTIONS))
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$(eval $(call assert_boolean,ENABLE_PLAT_COMPAT))
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$(eval $(call assert_boolean,ENABLE_PMF))
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@ -495,6 +496,7 @@ $(eval $(call add_define,ARM_GIC_ARCH))
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$(eval $(call add_define,COLD_BOOT_SINGLE_CPU))
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$(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS))
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$(eval $(call add_define,CTX_INCLUDE_FPREGS))
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$(eval $(call add_define,ENABLE_AMU))
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$(eval $(call add_define,ENABLE_ASSERTIONS))
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$(eval $(call add_define,ENABLE_PLAT_COMPAT))
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$(eval $(call add_define,ENABLE_PMF))
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@ -50,6 +50,10 @@ ifeq (${ENABLE_SPE_FOR_LOWER_ELS},1)
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BL31_SOURCES += lib/extensions/spe/spe.c
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endif
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ifeq (${ENABLE_AMU},1)
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BL31_SOURCES += lib/extensions/amu/aarch64/amu.c
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endif
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BL31_LINKERFILE := bl31/bl31.ld.S
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# Flag used to indicate if Crash reporting via console should be included
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -22,6 +22,10 @@ ifeq (${ENABLE_PMF}, 1)
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BL32_SOURCES += lib/pmf/pmf_main.c
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endif
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ifeq (${ENABLE_AMU}, 1)
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BL32_SOURCES += lib/extensions/amu/aarch32/amu.c
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endif
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BL32_LINKERFILE := bl32/sp_min/sp_min.ld.S
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# Include the platform-specific SP_MIN Makefile
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@ -321,6 +321,11 @@ Common build options
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payload. Please refer to the "Booting an EL3 payload" section for more
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details.
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- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
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This is an optional architectural feature available on v8.4 onwards. Some
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v8.2 implementations also implement an AMU and this option can be used to
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enable this feature on those systems as well. Default is 0.
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- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
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are compiled out. For debug builds, this option defaults to 1, and calls to
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``assert()`` are left in place. For release builds, this option defaults to 0
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@ -78,6 +78,11 @@
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/* CSSELR definitions */
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#define LEVEL_SHIFT 1
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/* ID_PFR0 definitions */
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#define ID_PFR0_AMU_SHIFT U(20)
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#define ID_PFR0_AMU_LENGTH U(4)
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#define ID_PFR0_AMU_MASK U(0xf)
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/* ID_PFR1 definitions */
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#define ID_PFR1_VIRTEXT_SHIFT 12
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#define ID_PFR1_VIRTEXT_MASK 0xf
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@ -187,6 +192,7 @@
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/* HCPTR definitions */
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#define HCPTR_RES1 ((1 << 13) | (1<<12) | 0x3ff)
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#define TCPAC_BIT (1 << 31)
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#define TAM_BIT (1 << 30)
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#define TTA_BIT (1 << 20)
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#define TCP11_BIT (1 << 10)
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#define TCP10_BIT (1 << 10)
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@ -407,6 +413,7 @@
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#define DCISW p15, 0, c7, c6, 2
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#define CTR p15, 0, c0, c0, 1
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#define CNTFRQ p15, 0, c14, c0, 0
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#define ID_PFR0 p15, 0, c0, c1, 0
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#define ID_PFR1 p15, 0, c0, c1, 1
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#define MAIR0 p15, 0, c10, c2, 0
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#define MAIR1 p15, 0, c10, c2, 1
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@ -525,4 +532,28 @@
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#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
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/*******************************************************************************
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* Definitions for system register interface to AMU for ARMv8.4 onwards
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******************************************************************************/
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#define AMCR p15, 0, c13, c2, 0
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#define AMCFGR p15, 0, c13, c2, 1
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#define AMCGCR p15, 0, c13, c2, 2
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#define AMUSERENR p15, 0, c13, c2, 3
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#define AMCNTENCLR0 p15, 0, c13, c2, 4
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#define AMCNTENSET0 p15, 0, c13, c2, 5
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#define AMCNTENCLR1 p15, 0, c13, c3, 0
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#define AMCNTENSET1 p15, 0, c13, c1, 1
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/* Activity Monitor Group 0 Event Counter Registers */
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#define AMEVCNTR00 p15, 0, c0
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#define AMEVCNTR01 p15, 1, c0
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#define AMEVCNTR02 p15, 2, c0
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#define AMEVCNTR03 p15, 3, c0
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/* Activity Monitor Group 0 Event Type Registers */
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#define AMEVTYPER00 p15, 0, c13, c6, 0
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#define AMEVTYPER01 p15, 0, c13, c6, 1
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#define AMEVTYPER02 p15, 0, c13, c6, 2
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#define AMEVTYPER03 p15, 0, c13, c6, 3
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#endif /* __ARCH_H__ */
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@ -227,6 +227,7 @@ DEFINE_SYSREG_RW_FUNCS(cpsr)
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******************************************************************************/
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DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR)
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DEFINE_COPROCR_READ_FUNC(midr, MIDR)
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DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0)
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DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1)
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DEFINE_COPROCR_READ_FUNC(isr, ISR)
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DEFINE_COPROCR_READ_FUNC(clidr, CLIDR)
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@ -281,6 +282,11 @@ DEFINE_COPROCR_RW_FUNCS(prrr, PRRR)
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DEFINE_COPROCR_RW_FUNCS(nmrr, NMRR)
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DEFINE_COPROCR_RW_FUNCS(dacr, DACR)
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DEFINE_COPROCR_RW_FUNCS(amcntenset0, AMCNTENSET0)
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DEFINE_COPROCR_RW_FUNCS(amcntenset1, AMCNTENSET1)
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DEFINE_COPROCR_RW_FUNCS(amcntenclr0, AMCNTENCLR0)
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DEFINE_COPROCR_RW_FUNCS(amcntenclr1, AMCNTENCLR1)
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/*
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* TLBI operation prototypes
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*/
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@ -110,6 +110,9 @@
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#define ID_AA64PFR0_EL1_SHIFT U(4)
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#define ID_AA64PFR0_EL2_SHIFT U(8)
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#define ID_AA64PFR0_EL3_SHIFT U(12)
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#define ID_AA64PFR0_AMU_SHIFT U(44)
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#define ID_AA64PFR0_AMU_LENGTH U(4)
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#define ID_AA64PFR0_AMU_MASK U(0xf)
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#define ID_AA64PFR0_ELX_MASK U(0xf)
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/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
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@ -295,6 +298,7 @@
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/* CPTR_EL3 definitions */
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#define TCPAC_BIT (U(1) << 31)
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#define TAM_BIT (U(1) << 30)
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#define TTA_BIT (U(1) << 20)
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#define TFP_BIT (U(1) << 10)
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#define CPTR_EL3_RESET_VAL U(0x0)
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@ -302,6 +306,7 @@
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/* CPTR_EL2 definitions */
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#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
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#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
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#define CPTR_EL2_TAM_BIT (U(1) << 30)
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#define CPTR_EL2_TTA_BIT (U(1) << 20)
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#define CPTR_EL2_TFP_BIT (U(1) << 10)
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#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
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@ -610,4 +615,28 @@
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******************************************************************************/
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#define PMBLIMITR_EL1 S3_0_C9_C10_0
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/*******************************************************************************
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* Definitions for system register interface to AMU for ARMv8.4 onwards
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******************************************************************************/
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#define AMCR_EL0 S3_3_C13_C2_0
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#define AMCFGR_EL0 S3_3_C13_C2_1
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#define AMCGCR_EL0 S3_3_C13_C2_2
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#define AMUSERENR_EL0 S3_3_C13_C2_3
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#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
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#define AMCNTENSET0_EL0 S3_3_C13_C2_5
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#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
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#define AMCNTENSET1_EL0 S3_3_C13_C3_1
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/* Activity Monitor Group 0 Event Counter Registers */
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#define AMEVCNTR00_EL0 S3_3_C13_C4_0
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#define AMEVCNTR01_EL0 S3_3_C13_C4_1
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#define AMEVCNTR02_EL0 S3_3_C13_C4_2
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#define AMEVCNTR03_EL0 S3_3_C13_C4_3
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/* Activity Monitor Group 0 Event Type Registers */
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#define AMEVTYPER00_EL0 S3_3_C13_C6_0
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#define AMEVTYPER01_EL0 S3_3_C13_C6_1
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#define AMEVTYPER02_EL0 S3_3_C13_C6_2
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#define AMEVTYPER03_EL0 S3_3_C13_C6_3
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#endif /* __ARCH_H__ */
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@ -322,6 +322,11 @@ DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
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DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
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DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
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#define IS_IN_EL(x) \
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@ -19,4 +19,38 @@
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/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
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#define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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******************************************************************************/
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#define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7
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#define CPUAMCNTENSET_EL0 S3_3_C15_C9_6
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#define CPUAMCFGR_EL0 S3_3_C15_C10_6
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#define CPUAMUSERENR_EL0 S3_3_C15_C10_7
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/* Activity Monitor Event Counter Registers */
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#define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0
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#define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1
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#define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2
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#define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3
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#define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4
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/* Activity Monitor Event Type Registers */
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#define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0
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#define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1
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#define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2
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#define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3
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#define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4
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#define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4)
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/*
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* The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are
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* fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are
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* programmable by programming the appropriate Event count bits in
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* CPUAMEVTYPER<n> register and are disabled by default. Platforms may
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* enable this with suitable programming.
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*/
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#define CORTEX_A75_AMU_GROUP0_MASK 0x7
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#define CORTEX_A75_AMU_GROUP1_MASK (0 << 3)
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#endif /* __CORTEX_A75_H__ */
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@ -0,0 +1,15 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __AMU_H__
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#define __AMU_H__
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/* Enable all group 0 counters */
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#define AMU_GROUP0_COUNTERS_MASK 0xf
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void amu_enable(int el2_unused);
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#endif /* __AMU_H__ */
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@ -11,6 +11,33 @@
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#include <plat_macros.S>
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#include <cortex_a75.h>
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func cortex_a75_reset_func
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
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msr actlr_el3, x0
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isb
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
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msr actlr_el2, x0
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isb
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/* Enable group0 counters */
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mov x0, #CORTEX_A75_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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isb
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/* Enable group1 counters */
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mov x0, #CORTEX_A75_AMU_GROUP1_MASK
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msr CPUAMCNTENSET_EL0, x0
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isb
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#endif
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ret
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endfunc cortex_a75_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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@ -47,5 +74,5 @@ func cortex_a75_cpu_reg_dump
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endfunc cortex_a75_cpu_reg_dump
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declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \
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CPU_NO_RESET_FUNC, \
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cortex_a75_reset_func, \
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cortex_a75_core_pwr_dwn
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@ -4,6 +4,7 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <amu.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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@ -132,6 +133,9 @@ static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t
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static void enable_extensions_nonsecure(int el2_unused)
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{
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#if IMAGE_BL32
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#if ENABLE_AMU
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amu_enable(el2_unused);
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#endif
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#endif
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}
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@ -4,6 +4,7 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <amu.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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@ -220,6 +221,10 @@ static void enable_extensions_nonsecure(int el2_unused)
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#if ENABLE_SPE_FOR_LOWER_ELS
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spe_enable(el2_unused);
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#endif
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#if ENABLE_AMU
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amu_enable(el2_unused);
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#endif
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#endif
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}
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@ -0,0 +1,32 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <amu.h>
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#include <arch.h>
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#include <arch_helpers.h>
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void amu_enable(int el2_unused)
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{
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uint64_t features;
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features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
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if ((features & ID_PFR0_AMU_MASK) == 1) {
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if (el2_unused) {
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uint64_t v;
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/*
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* Non-secure access from EL0 or EL1 to the Activity Monitor
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* registers do not trap to EL2.
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*/
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v = read_hcptr();
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v &= ~TAM_BIT;
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write_hcptr(v);
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}
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/* Enable group 0 counters */
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write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
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}
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}
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@ -0,0 +1,40 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <amu.h>
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#include <arch.h>
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#include <arch_helpers.h>
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void amu_enable(int el2_unused)
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{
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uint64_t features;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT;
|
||||
if ((features & ID_AA64PFR0_AMU_MASK) == 1) {
|
||||
uint64_t v;
|
||||
|
||||
if (el2_unused) {
|
||||
/*
|
||||
* CPTR_EL2.TAM: Set to zero so any accesses to
|
||||
* the Activity Monitor registers do not trap to EL2.
|
||||
*/
|
||||
v = read_cptr_el2();
|
||||
v &= ~CPTR_EL2_TAM_BIT;
|
||||
write_cptr_el2(v);
|
||||
}
|
||||
|
||||
/*
|
||||
* CPTR_EL3.TAM: Set to zero so that any accesses to
|
||||
* the Activity Monitor registers do not trap to EL3.
|
||||
*/
|
||||
v = read_cptr_el3();
|
||||
v &= ~TAM_BIT;
|
||||
write_cptr_el3(v);
|
||||
|
||||
/* Enable group 0 counters */
|
||||
write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);
|
||||
}
|
||||
}
|
||||
|
|
@ -156,3 +156,5 @@ ENABLE_SPE_FOR_LOWER_ELS := 1
|
|||
ifeq (${ARCH},aarch32)
|
||||
override ENABLE_SPE_FOR_LOWER_ELS := 0
|
||||
endif
|
||||
|
||||
ENABLE_AMU := 0
|
||||
|
|
|
|||
|
|
@ -147,6 +147,9 @@ BL31_SOURCES += drivers/arm/smmu/smmu_v3.c \
|
|||
# Disable the PSCI platform compatibility layer
|
||||
ENABLE_PLAT_COMPAT := 0
|
||||
|
||||
# Enable Activity Monitor Unit extensions by default
|
||||
ENABLE_AMU := 1
|
||||
|
||||
ifneq (${ENABLE_STACK_PROTECTOR},0)
|
||||
PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue