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Reserve some DDR DRAM for secure use on FVP platforms 

TZC-400 is configured to set the last 16MB of DRAM1 as secure memory and
the rest of DRAM as non-secure. Non-secure software must not attempt to
access the 16MB secure area.

Device tree files (sources and binaries) have been updated to match this
configuration, removing that memory from the Linux physical memory map.

To use UEFI and Linux with this patch, the latest version of UEFI and
the updated device tree files are required. Check the user guide in the
documentation for more details.

Replaced magic numbers with #define for memory region definition in the
platform security initialization function.

Fixes ARM-software/tf-issues#149

Change-Id: Ia5d070244aae6c5288ea0e6c8e89d92859522bfe
This commit is contained in:
Juan Castillo 2014-05-16 15:33:15 +01:00
parent dbad1bacba
commit 364daf9320
17 changed files with 31 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/user-guide.md
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@ -280,7 +280,7 @@ and Foundation FVPs:
git clone -n https://github.com/tianocore/edk2.git
cd edk2
git checkout c1cdcab9526506673b882017845a043cead8bc69
git checkout 129ff94661bd3a6c759b1e154c143d0136bedc7d
To build the software to be compatible with Foundation and Base FVPs, follow

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fdts/fvp-base-gicv2-psci.dtb
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2
fdts/fvp-base-gicv2-psci.dts
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@ -115,7 +115,7 @@
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
reg = <0x00000000 0x80000000 0 0x7F000000>,
<0x00000008 0x80000000 0 0x80000000>;
};

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fdts/fvp-base-gicv2legacy-psci.dtb
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2
fdts/fvp-base-gicv2legacy-psci.dts
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@ -115,7 +115,7 @@
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
reg = <0x00000000 0x80000000 0 0x7F000000>,
<0x00000008 0x80000000 0 0x80000000>;
};

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fdts/fvp-base-gicv3-psci.dtb
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2
fdts/fvp-base-gicv3-psci.dts
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@ -115,7 +115,7 @@
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
reg = <0x00000000 0x80000000 0 0x7F000000>,
<0x00000008 0x80000000 0 0x80000000>;
};

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fdts/fvp-foundation-gicv2-psci.dtb
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2
fdts/fvp-foundation-gicv2-psci.dts
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@ -91,7 +91,7 @@
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
reg = <0x00000000 0x80000000 0 0x7F000000>,
<0x00000008 0x80000000 0 0x80000000>;
};

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fdts/fvp-foundation-gicv2legacy-psci.dtb
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fdts/fvp-foundation-gicv2legacy-psci.dts
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@ -91,7 +91,7 @@
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
reg = <0x00000000 0x80000000 0 0x7F000000>,
<0x00000008 0x80000000 0 0x80000000>;
};

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fdts/fvp-foundation-gicv3-psci.dtb
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2
fdts/fvp-foundation-gicv3-psci.dts
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@ -91,7 +91,7 @@
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>,
reg = <0x00000000 0x80000000 0 0x7F000000>,
<0x00000008 0x80000000 0 0x80000000>;
};

2
plat/fvp/aarch64/plat_common.c
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@ -122,7 +122,7 @@ const mmap_region_t fvp_mmap[] = {
{ DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
/* 2nd GB as device for now...*/
{ 0x40000000, 0x40000000, MT_DEVICE | MT_RW | MT_SECURE },
{ DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS },
{ DRAM1_BASE, DRAM1_SIZE, MT_MEMORY | MT_RW | MT_NS },
{0}
};

4
plat/fvp/bl2_plat_setup.c
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@ -285,9 +285,9 @@ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
{
bl33_meminfo->total_base = DRAM_BASE;
bl33_meminfo->total_size = DRAM_SIZE;
bl33_meminfo->total_size = DRAM_SIZE - DRAM1_SEC_SIZE;
bl33_meminfo->free_base = DRAM_BASE;
bl33_meminfo->free_size = DRAM_SIZE;
bl33_meminfo->free_size = DRAM_SIZE - DRAM1_SEC_SIZE;
bl33_meminfo->attr = 0;
bl33_meminfo->attr = 0;
}

11
plat/fvp/plat_security.c
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@ -100,16 +100,23 @@ void plat_security_setup(void)
/* Set to cover the first block of DRAM */
tzc_configure_region(&controller, FILTER_SHIFT(0), 1,
DRAM_BASE, 0xFFFFFFFF, TZC_REGION_S_NONE,
DRAM1_BASE, DRAM1_END - DRAM1_SEC_SIZE,
TZC_REGION_S_NONE,
TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD));
/* Set to cover the secure reserved region */
tzc_configure_region(&controller, FILTER_SHIFT(0), 3,
(DRAM1_END - DRAM1_SEC_SIZE) + 1 , DRAM1_END,
TZC_REGION_S_RDWR,
0x0);
/* Set to cover the second block of DRAM */
tzc_configure_region(&controller, FILTER_SHIFT(0), 2,
0x880000000, 0xFFFFFFFFF, TZC_REGION_S_NONE,
DRAM2_BASE, DRAM2_END, TZC_REGION_S_NONE,
TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) |
TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) |

15
plat/fvp/platform.h
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@ -68,7 +68,7 @@
/* Non-Trusted Firmware BL33 and its load address */
#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
#define NS_IMAGE_OFFSET (DRAM_BASE + 0x8000000) /* DRAM + 128MB */
#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
/* Firmware Image Package */
#define FIP_IMAGE_NAME "fip.bin"
@ -139,8 +139,17 @@
#define PARAMS_BASE TZDRAM_BASE
#define DRAM_BASE 0x80000000ull
#define DRAM_SIZE 0x80000000ull
#define DRAM1_BASE 0x80000000ull
#define DRAM1_SIZE 0x80000000ull
#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1)
#define DRAM1_SEC_SIZE 0x01000000ull
#define DRAM_BASE DRAM1_BASE
#define DRAM_SIZE DRAM1_SIZE
#define DRAM2_BASE 0x880000000ull
#define DRAM2_SIZE 0x780000000ull
#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1)
#define PCIE_EXP_BASE 0x40000000
#define TZRNG_BASE 0x7fe60000