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Merge changes from topic "st_fixes" into integration 

* changes:
  fix(plat/st): correct IO compensation disabling
  fix(plat/st): correct BSEC error code management
  fix(drivers/st/pmic): missing error check
  fix(drivers/st/pmic): initialize i2c_state
  fix(drivers/st/clk): use correct return value
This commit is contained in:
Mark Dykes 2021-07-01 17:23:30 +02:00 committed by TrustedFirmware Code Review
parent 156a6e137c c2d18ca80f
commit 365e0f7764
6 changed files with 24 additions and 15 deletions
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4
drivers/st/clk/stm32mp1_clk.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
* Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@ -1737,7 +1737,7 @@ int stm32mp1_clk_init(void)
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return false;
return -FDT_ERR_NOTFOUND;
}
/* Check status field to disable security */

6
drivers/st/pmic/stm32mp_pmic.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -121,6 +121,9 @@ int dt_pmic_configure_boot_on_regulators(void)
}
regulators_node = fdt_subnode_offset(fdt, pmic_node, "regulators");
if (regulators_node < 0) {
return -ENOENT;
}
fdt_for_each_subnode(regulator_node, fdt, regulators_node) {
const fdt32_t *cuint;
@ -204,6 +207,7 @@ bool initialize_pmic_i2c(void)
i2c->i2c_base_addr = i2c_info.base;
i2c->dt_status = i2c_info.status;
i2c->clock = i2c_info.clock;
i2c->i2c_state = I2C_STATE_RESET;
i2c_init.own_address1 = pmic_i2c_addr;
i2c_init.addressing_mode = I2C_ADDRESSINGMODE_7BIT;
i2c_init.dual_address_mode = I2C_DUALADDRESS_DISABLE;

8
plat/st/stm32mp1/include/stm32mp1_smc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -58,4 +58,10 @@
#define STM32_SMC_WRITE_SHADOW 0x03
#define STM32_SMC_READ_OTP 0x04
/* SMC error codes */
#define STM32_SMC_OK 0x00000000U
#define STM32_SMC_NOT_SUPPORTED 0xFFFFFFFFU
#define STM32_SMC_FAILED 0xFFFFFFFEU
#define STM32_SMC_INVALID_PARAMS 0xFFFFFFFDU
#endif /* STM32MP1_SMC_H */

11
plat/st/stm32mp1/services/bsec_svc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2016-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -28,11 +28,11 @@ uint32_t bsec_main(uint32_t x1, uint32_t x2, uint32_t x3,
result = bsec_program_otp(x3, x2);
break;
case STM32_SMC_WRITE_SHADOW:
*ret_otp_value = 0;
*ret_otp_value = 0U;
result = bsec_write_otp(x3, x2);
break;
case STM32_SMC_READ_OTP:
*ret_otp_value = 0;
*ret_otp_value = 0U;
result = bsec_read_otp(&tmp_data, x2);
if (result != BSEC_OK) {
break;
@ -52,9 +52,8 @@ uint32_t bsec_main(uint32_t x1, uint32_t x2, uint32_t x3,
break;
default:
result = BSEC_ERROR;
break;
return STM32_SMC_INVALID_PARAMS;
}
return result;
return (result == BSEC_OK) ? STM32_SMC_OK : STM32_SMC_FAILED;
}

4
plat/st/stm32mp1/services/stm32mp1_svc_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2014-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -75,7 +75,7 @@ static uintptr_t stm32mp1_svc_smc_handler(uint32_t smc_fid, u_register_t x1,
default:
WARN("Unimplemented STM32MP1 Service Call: 0x%x\n", smc_fid);
ret1 = SMC_UNK;
ret1 = STM32_SMC_NOT_SUPPORTED;
break;
}

6
plat/st/stm32mp1/stm32mp1_syscfg.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
* Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -22,6 +22,7 @@
#define SYSCFG_ICNR 0x1CU
#define SYSCFG_CMPCR 0x20U
#define SYSCFG_CMPENSETR 0x24U
#define SYSCFG_CMPENCLRR 0x28U
/*
* SYSCFG_BOOTR Register
@ -167,8 +168,7 @@ void stm32mp1_syscfg_disable_io_compensation(void)
mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL);
mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
SYSCFG_CMPENSETR_MPU_EN);
mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENCLRR, SYSCFG_CMPENSETR_MPU_EN);
stm32mp1_clk_disable_non_secure(SYSCFG);
}