From 37ac9b7f11ee803fb128203a4edabcad99c0e466 Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Thu, 30 May 2019 13:58:53 +0100 Subject: [PATCH] plat: imx8mm: Add initial defintions to facilitate FIP layout Adds a number of definitions consistent with the established WaRP7 equivalents specifying number of io_handles and block devices. Signed-off-by: Bryan O'Donoghue Signed-off-by: Ying-Chun Liu (PaulLiu) Change-Id: If1d7ef1ad3ac3dfc860f949392c7534ce8d206e3 --- plat/imx/imx8m/imx8mm/include/platform_def.h | 24 +++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index 1041459c8..ec915ad68 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -1,9 +1,11 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include + #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 @@ -34,11 +36,27 @@ #define PLAT_SDEI_NORMAL_PRI 0x20 #define PLAT_SDEI_SGI_PRIVATE U(9) +#if defined(NEED_BL2) +#define BL2_BASE U(0x920000) +#define BL2_LIMIT U(0x940000) +#define BL31_BASE U(0x900000) +#define BL31_LIMIT U(0x920000) +#define IMX8MM_FIP_BASE U(0x40310000) +#define IMX8MM_FIP_SIZE U(0x000200000) +#define IMX8MM_FIP_LIMIT U(FIP_BASE + FIP_SIZE) + +/* Define FIP image location on eMMC */ +#define IMX8MM_FIP_MMC_BASE U(0x100000) + +#define PLAT_IMX8MM_BOOT_MMC_BASE U(0x30B50000) /* SD */ +#else #define BL31_BASE U(0x920000) #define BL31_LIMIT U(0x940000) +#endif /* non-secure uboot base */ #define PLAT_NS_IMAGE_OFFSET U(0x40200000) +#define PLAT_NS_IMAGE_SIZE U(0x00100000) /* GICv3 base address */ #define PLAT_GICD_BASE U(0x38800000) @@ -127,3 +145,7 @@ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ #define IMX_WDOG_B_RESET + +#define MAX_IO_HANDLES 3U +#define MAX_IO_DEVICES 2U +#define MAX_IO_BLOCK_DEVICES 1U