marvell: Move BLE from external repo to the platform folder
The BLE is the pre-TF-A boot stage required by Marvell Armada BootROM for bringing up DRAM and allow the boot image copy to it. Since this is not a standard boot level and only uses the TF-A as a build environment, it was introduced out of source tree. However it turns out that such remote location introduces additional complexity to the upstream TF-A build process. In order to simplify the build environment the BLE source folder is relocated from the external repository to A8K platform directory. The build documentation is updated accordingly. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
This commit is contained in:
Konstantin Porotchkin
parent
a4277cda5c
commit
37c4341b10
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@ -63,8 +63,7 @@ Build Instructions
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- BLE_PATH:
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Points to BLE (Binary ROM extension) sources folder. Only required for A8K builds.
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The parameter is optional, its default value is "ble".
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For the BLE source location, check the section "Tools and external components installation"
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The parameter is optional, its default value is "plat/marvell/a8k/common/ble".
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- MV_DDR_PATH:
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For A7/8K, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0,
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@ -138,7 +137,7 @@ Special Build Flags
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--------------------
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- PLAT_RECOVERY_IMAGE_ENABLE: When set this option to enable secondary recovery function when build
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atf. In order to build UART recovery image this operation should be disabled for a70x0 and a80x0
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because of hardware limitation (boot from secondary image can interrupt UART recovery process).
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because of hardware limitation (boot from secondary image can interrupt UART recovery process).
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This MACRO definition is set in plat/marvell/a8k/common/include/platform_def.h file
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(for more information about build options, please refer to section 'Summary of build options' in TF-A user-guide:
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@ -184,14 +183,10 @@ Armada37x0 Builds require installation of 3 components
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(3) Armada3700 tools available at the following repository (use the latest release branch)::
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https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
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Armada70x0 and Armada80x0 Builds require installation of 2 components
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---------------------------------------------------------------------
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Armada70x0 and Armada80x0 Builds require installation of an additional component
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--------------------------------------------------------------------------------
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(1) DDR initialization library sources (mv_ddr) available at the following repository
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(use the "mv_ddr-armada-atf-mainline" branch)::
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https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
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(2) BLE sources available at the following repository (use the "atf-mainline" branch)::
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https://github.com/MarvellEmbeddedProcessors/ble-marvell.git
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@ -106,7 +106,7 @@ endif
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include $(PLAT_COMMON_BASE)/mss/mss_a8k.mk
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# BLE (ROM context execution code, AKA binary extension)
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BLE_PATH ?= ble
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BLE_PATH ?= $(PLAT_COMMON_BASE)/ble
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include ${BLE_PATH}/ble.mk
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$(eval $(call MAKE_BL,e))
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@ -0,0 +1,76 @@
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <platform_def.h>
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OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
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OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(ble_main)
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MEMORY {
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RAM (rwx): ORIGIN = BLE_BASE, LENGTH = BLE_LIMIT - BLE_BASE
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}
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SECTIONS
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{
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. = BLE_BASE;
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ro . : {
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__RO_START__ = .;
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*ble_main.o(.entry*)
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*(.text*)
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*(.rodata*)
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__RO_END_UNALIGNED__ = .;
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__RO_END__ = .;
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} >RAM
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/*
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* Define a linker symbol to mark start of the RW memory area for this
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* image.
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*/
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__RW_START__ = . ;
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.data . : {
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__DATA_START__ = .;
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*(.data*)
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__DATA_END__ = .;
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} >RAM
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stacks . (NOLOAD) : {
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__STACKS_START__ = .;
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*(tzfw_normal_stacks)
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__STACKS_END__ = .;
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} >RAM
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.bss : {
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__BSS_START__ = .;
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*(.bss*)
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__BSS_END__ = .;
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} >RAM
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/*
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* Extend the BLE binary to the maximum size allocated for it in platform
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* definition files and prevent overlapping between BLE BSS section and
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* additional extensions that can follow the BLE in flash image preamble.
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* This situation happens for instance when secure extension is added to
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* the image preamble.
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*/
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.fill LOADADDR(.bss) + SIZEOF(.bss) : {
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FILL(0xDEADC0DE);
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. = ORIGIN(RAM) + LENGTH(RAM) - 1;
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BYTE(0x00)
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} >RAM
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/*
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* Define a linker symbol to mark end of the RW memory area for this
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* image.
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*/
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__RW_END__ = .;
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__BLE_END__ = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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}
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@ -0,0 +1,31 @@
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# Copyright (C) 2018 Marvell International Ltd.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# https://spdx.org/licenses
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MV_DDR_PATH ?= drivers/marvell/mv_ddr
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MV_DDR_LIB = $(CURDIR)/$(BUILD_PLAT)/ble/mv_ddr_lib.a
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LIBC_LIB = $(CURDIR)/$(BUILD_PLAT)/lib/libc.a
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BLE_LIBS = $(MV_DDR_LIB) $(LIBC_LIB)
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PLAT_MARVELL = plat/marvell
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BLE_SOURCES += $(BLE_PATH)/ble_main.c \
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$(BLE_PATH)/ble_mem.S \
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drivers/delay_timer/delay_timer.c \
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$(PLAT_MARVELL)/common/plat_delay_timer.c
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PLAT_INCLUDES += -I$(MV_DDR_PATH) \
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-I$(CURDIR)/include/ \
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-I$(CURDIR)/include/drivers \
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-I$(CURDIR)/include/lib \
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-I$(CURDIR)/include/lib/libc \
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-I$(CURDIR)/include/lib/libc/aarch64 \
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-I$(CURDIR)/drivers/marvell
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BLE_LINKERFILE := $(BLE_PATH)/ble.ld.S
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FORCE:
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$(MV_DDR_LIB): FORCE
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@+make -C $(MV_DDR_PATH) --no-print-directory PLAT_INCLUDES="$(PLAT_INCLUDES)" PLATFORM=$(PLAT) ARCH=AARCH64 OBJ_DIR=$(CURDIR)/$(BUILD_PLAT)/ble
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@ -0,0 +1,98 @@
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <arch_helpers.h>
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#include <debug.h>
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#include <console.h>
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#include <marvell_plat_priv.h>
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#include <marvell_pm.h>
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#include <platform_def.h>
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#include <plat_marvell.h>
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#include <string.h>
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#define BR_FLAG_SILENT 0x1
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#define SKIP_IMAGE_CODE 0xDEADB002
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void mailbox_clean(void)
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{
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uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE;
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memset(mailbox, 0, PLAT_MARVELL_MAILBOX_SIZE);
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}
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int exec_ble_main(int bootrom_flags)
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{
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int skip = 0;
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uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE;
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/*
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* In some situations, like boot from UART, bootrom will
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* request to avoid printing to console. in that case don't
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* initialize the console and prints will be ignored
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*/
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if ((bootrom_flags & BR_FLAG_SILENT) == 0)
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console_init(PLAT_MARVELL_BOOT_UART_BASE,
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PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
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MARVELL_CONSOLE_BAUDRATE);
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NOTICE("Starting binary extension\n");
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/* initiliaze time (for delay functionality) */
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plat_delay_timer_init();
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ble_plat_setup(&skip);
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/* if there's skip image request, bootrom will load from the image
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* saved on the next address of the flash
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*/
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if (skip)
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return SKIP_IMAGE_CODE;
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/*
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* Check if the mailbox magic number is stored at index MBOX_IDX_MAGIC
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* and the suspend to RAM magic number at index MBOX_IDX_SUSPEND_MAGIC.
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* If the above is true, this is the recovery from suspend to RAM state.
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* In such case the mailbox should remain intact, since it stores the
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* warm boot jump address to be used by the TF-A in BL31.
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* Othervise the mailbox should be cleaned from a garbage data.
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*/
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if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM ||
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mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE) {
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NOTICE("Cold boot\n");
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mailbox_clean();
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} else {
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void (*bootrom_exit)(void) =
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(void (*)(void))mailbox[MBOX_IDX_ROM_EXIT_ADDR];
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INFO("Recovery...\n");
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/*
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* If this is recovery from suspend, two things has to be done:
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* 1. Define the DRAM region as executable memory for preparing
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* jump to TF-A
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* 2. Instead of returning control to the BootROM, invalidate
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* and flush caches, and continue execution at address stored
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* in the mailbox.
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* This should be done until the BootROM have a native support
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* for the system restore flow.
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*/
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marvell_ble_prepare_exit();
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bootrom_exit();
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}
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return 0;
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}
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/* NOTE: don't notify this function, all code must be added to exec_ble_main
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* in order to keep the end of ble_main as a fixed address.
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*/
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int __attribute__ ((section(".entry"))) ble_main(int bootrom_flags)
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{
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volatile int ret;
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ret = exec_ble_main(bootrom_flags);
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return ret;
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}
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@ -0,0 +1,30 @@
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <asm_macros.S>
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#include <marvell_def.h>
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#include <platform_def.h>
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#define PTE_NON_EXEC_OFF 54 /* XN - eXecute Never bit offset - see VMSAv8-64 */
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.globl marvell_ble_prepare_exit
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func marvell_ble_prepare_exit
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/*
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* Read the page table base and set the first page to be executable.
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* This is required for jumping to DRAM for further execution.
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*/
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mrs x0, ttbr0_el3
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ldr x1, [x0]
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mov x2, #1
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bic x1, x1, x2, lsl #PTE_NON_EXEC_OFF
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str x1, [x0]
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tlbi alle3
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dsb sy
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isb
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ret
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endfunc marvell_ble_prepare_exit
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