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Merge pull request #1821 from Yann-lms/stm32mp1_2019-02-14 

Series of new patches for STM32MP1
This commit is contained in:
Antonio Niño Díaz 2019-02-18 10:51:57 +00:00 committed by GitHub
parent 833216666f 6c1e71e1a1
commit 37cdad2a76
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
46 changed files with 3230 additions and 2062 deletions
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1294
drivers/st/clk/stm32mp1_clk.c
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File diff suppressed because it is too large Load Diff

251
drivers/st/clk/stm32mp1_clkfunc.c
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@ -10,17 +10,12 @@
#include <platform_def.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp_clkfunc.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_clkfunc.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#define DT_RCC_NODE_NAME "rcc@50000000"
#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
#define DT_RCC_COMPAT "syscon"
#define DT_STGEN_COMPAT "st,stm32-stgen"
#define DT_UART_COMPAT "st,stm32h7-uart"
#define DT_USART_COMPAT "st,stm32h7-usart"
const char *stm32mp_osc_node_label[NB_OSC] = {
[_LSI] = "clk-lsi",
[_LSE] = "clk-lse",
@ -28,23 +23,14 @@ const char *stm32mp_osc_node_label[NB_OSC] = {
[_HSE] = "clk-hse",
[_CSI] = "clk-csi",
[_I2S_CKIN] = "i2s_ckin",
[_USB_PHY_48] = "ck_usbo_48m"
};
/*******************************************************************************
* This function returns the RCC node in the device tree.
******************************************************************************/
static int fdt_get_rcc_node(void *fdt)
{
return fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
}
/*******************************************************************************
* This function reads the frequency of an oscillator from its name.
* It reads the value indicated inside the device tree.
* Returns 0 on success, and a negative FDT/ERRNO error code on failure.
* On success, value is stored in the second parameter.
******************************************************************************/
/*
* Get the frequency of an oscillator from its name in device tree.
* @param name: oscillator name
* @param freq: stores the frequency of the oscillator
* @return: 0 on success, and a negative FDT/ERRNO error code on failure.
*/
int fdt_osc_read_freq(const char *name, uint32_t *freq)
{
int node, subnode;
@ -88,11 +74,12 @@ int fdt_osc_read_freq(const char *name, uint32_t *freq)
return 0;
}
/*******************************************************************************
* This function checks the presence of an oscillator property from its id.
* The search is done inside the device tree.
* Returns true/false regarding search result.
******************************************************************************/
/*
* Check the presence of an oscillator property from its id.
* @param osc_id: oscillator ID
* @param prop_name: property name
* @return: true/false regarding search result.
*/
bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name)
{
int node, subnode;
@ -133,11 +120,13 @@ bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name)
return false;
}
/*******************************************************************************
* This function reads a value of a oscillator property from its id.
* Returns value on success, and a default value if property not found.
* Default value is passed as parameter.
******************************************************************************/
/*
* Get the value of a oscillator property from its ID.
* @param osc_id: oscillator ID
* @param prop_name: property name
* @param dflt_value: default value
* @return oscillator value on success, default value if property not found.
*/
uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
const char *prop_name, uint32_t dflt_value)
{
@ -176,201 +165,3 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
return dflt_value;
}
/*******************************************************************************
* This function reads the rcc base address.
* It reads the value indicated inside the device tree.
* Returns address if success, and 0 value else.
******************************************************************************/
uint32_t fdt_rcc_read_addr(void)
{
int node, subnode;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_path_offset(fdt, "/soc");
if (node < 0) {
return 0;
}
fdt_for_each_subnode(subnode, fdt, node) {
const char *cchar;
int ret;
cchar = fdt_get_name(fdt, subnode, &ret);
if (cchar == NULL) {
return 0;
}
if (strncmp(cchar, DT_RCC_NODE_NAME, (size_t)ret) == 0) {
const fdt32_t *cuint;
cuint = fdt_getprop(fdt, subnode, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
}
return 0;
}
/*******************************************************************************
* This function reads a series of parameters in rcc-clk section.
* It reads the values indicated inside the device tree, from property name.
* The number of parameters is also indicated as entry parameter.
* Returns 0 if success, and a negative value else.
* If success, values are stored at the second parameter address.
******************************************************************************/
int fdt_rcc_read_uint32_array(const char *prop_name,
uint32_t *array, uint32_t count)
{
int node;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
if (node < 0) {
return -FDT_ERR_NOTFOUND;
}
return fdt_read_uint32_array(node, prop_name, array, count);
}
/*******************************************************************************
* This function gets the subnode offset in rcc-clk section from its name.
* It reads the values indicated inside the device tree.
* Returns offset on success, and a negative FDT/ERRNO error code on failure.
******************************************************************************/
int fdt_rcc_subnode_offset(const char *name)
{
int node, subnode;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return -FDT_ERR_NOTFOUND;
}
subnode = fdt_subnode_offset(fdt, node, name);
if (subnode <= 0) {
return -FDT_ERR_NOTFOUND;
}
return subnode;
}
/*******************************************************************************
* This function gets the pointer to a rcc-clk property from its name.
* It reads the values indicated inside the device tree.
* Length of the property is stored in the second parameter.
* Returns pointer on success, and NULL value on failure.
******************************************************************************/
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp)
{
const fdt32_t *cuint;
int node, len;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return NULL;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return NULL;
}
cuint = fdt_getprop(fdt, node, prop_name, &len);
if (cuint == NULL) {
return NULL;
}
*lenp = len;
return cuint;
}
/*******************************************************************************
* This function gets the secure status for rcc node.
* It reads secure-status in device tree.
* Returns true if rcc is available from secure world, false if not.
******************************************************************************/
bool fdt_get_rcc_secure_status(void)
{
int node;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return false;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return false;
}
return (fdt_get_status(node) & DT_SECURE) != 0U;
}
/*******************************************************************************
* This function reads the stgen base address.
* It reads the value indicated inside the device tree.
* Returns address on success, and NULL value on failure.
******************************************************************************/
uintptr_t fdt_get_stgen_base(void)
{
int node;
const fdt32_t *cuint;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_node_offset_by_compatible(fdt, -1, DT_STGEN_COMPAT);
if (node < 0) {
return 0;
}
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/*******************************************************************************
* This function gets the clock ID of the given node.
* It reads the value indicated inside the device tree.
* Returns ID on success, and a negative FDT/ERRNO error code on failure.
******************************************************************************/
int fdt_get_clock_id(int node)
{
const fdt32_t *cuint;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
cuint = fdt_getprop(fdt, node, "clocks", NULL);
if (cuint == NULL) {
return -FDT_ERR_NOTFOUND;
}
cuint++;
return (int)fdt32_to_cpu(*cuint);
}

206
drivers/st/clk/stm32mp_clkfunc.c Normal file
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@ -0,0 +1,206 @@
/*
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
#include <libfdt.h>
#include <platform_def.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp_clkfunc.h>
#define DT_STGEN_COMPAT "st,stm32-stgen"
/*
* Get the RCC node offset from the device tree
* @param fdt: Device tree reference
* @return: Node offset or a negative value on error
*/
int fdt_get_rcc_node(void *fdt)
{
return fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
}
/*
* Get the RCC base address from the device tree
* @return: RCC address or 0 on error
*/
uint32_t fdt_rcc_read_addr(void)
{
int node;
void *fdt;
const fdt32_t *cuint;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return 0;
}
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/*
* Read a series of parameters in rcc-clk section in device tree
* @param prop_name: Name of the RCC property to be read
* @param array: the array to store the property parameters
* @param count: number of parameters to be read
* @return: 0 on succes or a negative value on error
*/
int fdt_rcc_read_uint32_array(const char *prop_name,
uint32_t *array, uint32_t count)
{
int node;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return -FDT_ERR_NOTFOUND;
}
return fdt_read_uint32_array(node, prop_name, array, count);
}
/*
* Get the subnode offset in rcc-clk section from its name in device tree
* @param name: name of the RCC property
* @return: offset on success, and a negative FDT/ERRNO error code on failure.
*/
int fdt_rcc_subnode_offset(const char *name)
{
int node, subnode;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return -FDT_ERR_NOTFOUND;
}
subnode = fdt_subnode_offset(fdt, node, name);
if (subnode <= 0) {
return -FDT_ERR_NOTFOUND;
}
return subnode;
}
/*
* Get the pointer to a rcc-clk property from its name.
* @param name: name of the RCC property
* @param lenp: stores the length of the property.
* @return: pointer to the property on success, and NULL value on failure.
*/
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp)
{
const fdt32_t *cuint;
int node, len;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return NULL;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return NULL;
}
cuint = fdt_getprop(fdt, node, prop_name, &len);
if (cuint == NULL) {
return NULL;
}
*lenp = len;
return cuint;
}
/*
* Get the secure status for rcc node in device tree.
* @return: true if rcc is available from secure world, false if not.
*/
bool fdt_get_rcc_secure_status(void)
{
int node;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return false;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return false;
}
return !!(fdt_get_status(node) & DT_SECURE);
}
/*
* Get the stgen base address.
* @return: address of stgen on success, and NULL value on failure.
*/
uintptr_t fdt_get_stgen_base(void)
{
int node;
const fdt32_t *cuint;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_node_offset_by_compatible(fdt, -1, DT_STGEN_COMPAT);
if (node < 0) {
return 0;
}
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/*
* Get the clock ID of the given node in device tree.
* @param node: node offset
* @return: Clock ID on success, and a negative FDT/ERRNO error code on failure.
*/
int fdt_get_clock_id(int node)
{
const fdt32_t *cuint;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return -ENOENT;
}
cuint = fdt_getprop(fdt, node, "clocks", NULL);
if (cuint == NULL) {
return -FDT_ERR_NOTFOUND;
}
cuint++;
return (int)fdt32_to_cpu(*cuint);
}

58
drivers/st/ddr/stm32mp1_ddr.c
View File

@ -14,13 +14,10 @@
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32mp_pmic.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_ddr.h>
#include <drivers/st/stm32mp1_ddr_regs.h>
#include <drivers/st/stm32mp1_pwr.h>
#include <drivers/st/stm32mp1_ram.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <lib/mmio.h>
#include <plat/common/platform.h>
@ -32,7 +29,7 @@ struct reg_desc {
#define INVALID_OFFSET 0xFFU
#define TIMESLOT_1US (plat_get_syscnt_freq2() / 1000000U)
#define TIMEOUT_US_1S 1000000U
#define DDRCTL_REG(x, y) \
{ \
@ -327,49 +324,43 @@ static void stm32mp1_ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
{
uint32_t pgsr;
int error = 0;
unsigned long start;
unsigned long time0, time;
start = get_timer(0);
time0 = start;
uint64_t timeout = timeout_init_us(TIMEOUT_US_1S);
do {
pgsr = mmio_read_32((uintptr_t)&phy->pgsr);
time = get_timer(start);
if (time != time0) {
VERBOSE(" > [0x%lx] pgsr = 0x%x &\n",
(uintptr_t)&phy->pgsr, pgsr);
VERBOSE(" [0x%lx] pir = 0x%x (time=%lx)\n",
(uintptr_t)&phy->pir,
mmio_read_32((uintptr_t)&phy->pir),
time);
}
time0 = time;
if (time > plat_get_syscnt_freq2()) {
VERBOSE(" > [0x%lx] pgsr = 0x%x &\n",
(uintptr_t)&phy->pgsr, pgsr);
if (timeout_elapsed(timeout)) {
panic();
}
if ((pgsr & DDRPHYC_PGSR_DTERR) != 0U) {
VERBOSE("DQS Gate Trainig Error\n");
error++;
}
if ((pgsr & DDRPHYC_PGSR_DTIERR) != 0U) {
VERBOSE("DQS Gate Trainig Intermittent Error\n");
error++;
}
if ((pgsr & DDRPHYC_PGSR_DFTERR) != 0U) {
VERBOSE("DQS Drift Error\n");
error++;
}
if ((pgsr & DDRPHYC_PGSR_RVERR) != 0U) {
VERBOSE("Read Valid Training Error\n");
error++;
}
if ((pgsr & DDRPHYC_PGSR_RVEIRR) != 0U) {
VERBOSE("Read Valid Training Intermittent Error\n");
error++;
}
} while ((pgsr & DDRPHYC_PGSR_IDONE) == 0U && error == 0);
} while (((pgsr & DDRPHYC_PGSR_IDONE) == 0U) && (error == 0));
VERBOSE("\n[0x%lx] pgsr = 0x%x\n",
(uintptr_t)&phy->pgsr, pgsr);
}
@ -401,21 +392,19 @@ static void stm32mp1_start_sw_done(struct stm32mp1_ddrctl *ctl)
/* Wait quasi dynamic register update */
static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
{
unsigned long start;
uint64_t timeout;
uint32_t swstat;
mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
VERBOSE("[0x%lx] swctl = 0x%x\n",
(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));
start = get_timer(0);
timeout = timeout_init_us(TIMEOUT_US_1S);
do {
swstat = mmio_read_32((uintptr_t)&ctl->swstat);
VERBOSE("[0x%lx] swstat = 0x%x ",
(uintptr_t)&ctl->swstat, swstat);
VERBOSE("timer in ms 0x%x = start 0x%lx\r",
get_timer(0), start);
if (get_timer(start) > plat_get_syscnt_freq2()) {
if (timeout_elapsed(timeout)) {
panic();
}
} while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U);
@ -427,22 +416,21 @@ static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
/* Wait quasi dynamic register update */
static void stm32mp1_wait_operating_mode(struct ddr_info *priv, uint32_t mode)
{
unsigned long start;
uint64_t timeout;
uint32_t stat;
uint32_t operating_mode;
uint32_t selref_type;
int break_loop = 0;
start = get_timer(0);
timeout = timeout_init_us(TIMEOUT_US_1S);
for ( ; ; ) {
uint32_t operating_mode;
uint32_t selref_type;
stat = mmio_read_32((uintptr_t)&priv->ctl->stat);
operating_mode = stat & DDRCTRL_STAT_OPERATING_MODE_MASK;
selref_type = stat & DDRCTRL_STAT_SELFREF_TYPE_MASK;
VERBOSE("[0x%lx] stat = 0x%x\n",
(uintptr_t)&priv->ctl->stat, stat);
VERBOSE("timer in ms 0x%x = start 0x%lx\r",
get_timer(0), start);
if (get_timer(start) > plat_get_syscnt_freq2()) {
if (timeout_elapsed(timeout)) {
panic();
}
@ -639,7 +627,7 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
*/
/* Change Bypass Mode Frequency Range */
if (stm32mp1_clk_get_rate(DDRPHYC) < 100000000U) {
if (stm32mp_clk_get_rate(DDRPHYC) < 100000000U) {
mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr,
DDRPHYC_DLLGCR_BPS200);
} else {
@ -712,7 +700,7 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
static int board_ddr_power_init(enum ddr_type ddr_type)
{
if (dt_check_pmic()) {
if (dt_pmic_status() > 0) {
return pmic_ddr_power_init(ddr_type);
}

9
drivers/st/ddr/stm32mp1_ddr_helpers.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,15 +7,18 @@
#include <platform_def.h>
#include <drivers/st/stm32mp1_ddr_helpers.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <lib/mmio.h>
void ddr_enable_clock(void)
{
mmio_setbits_32(RCC_BASE + RCC_DDRITFCR,
stm32mp1_clk_rcc_regs_lock();
mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR,
RCC_DDRITFCR_DDRC1EN |
RCC_DDRITFCR_DDRC2EN |
RCC_DDRITFCR_DDRPHYCEN |
RCC_DDRITFCR_DDRPHYCAPBEN |
RCC_DDRITFCR_DDRCAPBEN);
stm32mp1_clk_rcc_regs_unlock();
}

66
drivers/st/ddr/stm32mp1_ram.c
View File

@ -12,12 +12,9 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_ddr.h>
#include <drivers/st/stm32mp1_ddr_helpers.h>
#include <drivers/st/stm32mp1_ram.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <lib/mmio.h>
#define DDR_PATTERN 0xAAAAAAAAU
@ -31,7 +28,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
ddr_enable_clock();
ddrphy_clk = stm32mp1_clk_get_rate(DDRPHYC);
ddrphy_clk = stm32mp_clk_get_rate(DDRPHYC);
VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n",
mem_speed, ddrphy_clk / 1000U);
@ -65,10 +62,10 @@ static uint32_t ddr_test_data_bus(void)
uint32_t pattern;
for (pattern = 1U; pattern != 0U; pattern <<= 1) {
mmio_write_32(STM32MP1_DDR_BASE, pattern);
mmio_write_32(STM32MP_DDR_BASE, pattern);
if (mmio_read_32(STM32MP1_DDR_BASE) != pattern) {
return (uint32_t)STM32MP1_DDR_BASE;
if (mmio_read_32(STM32MP_DDR_BASE) != pattern) {
return (uint32_t)STM32MP_DDR_BASE;
}
}
@ -92,44 +89,44 @@ static uint32_t ddr_test_addr_bus(void)
/* Write the default pattern at each of the power-of-two offsets. */
for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
offset <<= 1) {
mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)offset,
mmio_write_32(STM32MP_DDR_BASE + (uint32_t)offset,
DDR_PATTERN);
}
/* Check for address bits stuck high. */
mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset,
mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
DDR_ANTIPATTERN);
for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
offset <<= 1) {
if (mmio_read_32(STM32MP1_DDR_BASE + (uint32_t)offset) !=
if (mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) !=
DDR_PATTERN) {
return (uint32_t)(STM32MP1_DDR_BASE + offset);
return (uint32_t)(STM32MP_DDR_BASE + offset);
}
}
mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN);
mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN);
/* Check for address bits stuck low or shorted. */
for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U;
testoffset <<= 1) {
mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset,
mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
DDR_ANTIPATTERN);
if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) {
return STM32MP1_DDR_BASE;
if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
return STM32MP_DDR_BASE;
}
for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
offset <<= 1) {
if ((mmio_read_32(STM32MP1_DDR_BASE +
if ((mmio_read_32(STM32MP_DDR_BASE +
(uint32_t)offset) != DDR_PATTERN) &&
(offset != testoffset)) {
return (uint32_t)(STM32MP1_DDR_BASE + offset);
return (uint32_t)(STM32MP_DDR_BASE + offset);
}
}
mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset,
mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
DDR_PATTERN);
}
@ -147,13 +144,13 @@ static uint32_t ddr_check_size(void)
{
uint32_t offset = sizeof(uint32_t);
mmio_write_32(STM32MP1_DDR_BASE, DDR_PATTERN);
mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN);
while (offset < STM32MP1_DDR_MAX_SIZE) {
mmio_write_32(STM32MP1_DDR_BASE + offset, DDR_ANTIPATTERN);
while (offset < STM32MP_DDR_MAX_SIZE) {
mmio_write_32(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN);
dsb();
if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) {
if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
break;
}
@ -171,7 +168,7 @@ static int stm32mp1_ddr_setup(void)
int ret;
struct stm32mp1_ddr_config config;
int node, len;
uint32_t tamp_clk_off = 0, uret, idx;
uint32_t uret, idx;
void *fdt;
#define PARAM(x, y) \
@ -240,19 +237,6 @@ static int stm32mp1_ddr_setup(void)
}
}
if (!stm32mp1_clk_is_enabled(RTCAPB)) {
tamp_clk_off = 1;
if (stm32mp1_clk_enable(RTCAPB) != 0) {
return -EINVAL;
}
}
if (tamp_clk_off != 0U) {
if (stm32mp1_clk_disable(RTCAPB) != 0) {
return -EINVAL;
}
}
/* Disable axidcg clock gating during init */
mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
@ -301,12 +285,12 @@ int stm32mp1_ddr_probe(void)
VERBOSE("STM32MP DDR probe\n");
priv->ctl = (struct stm32mp1_ddrctl *)DDRCTRL_BASE;
priv->phy = (struct stm32mp1_ddrphy *)DDRPHYC_BASE;
priv->pwr = PWR_BASE;
priv->rcc = RCC_BASE;
priv->ctl = (struct stm32mp1_ddrctl *)stm32mp_ddrctrl_base();
priv->phy = (struct stm32mp1_ddrphy *)stm32mp_ddrphyc_base();
priv->pwr = stm32mp_pwr_base();
priv->rcc = stm32mp_rcc_base();
priv->info.base = STM32MP1_DDR_BASE;
priv->info.base = STM32MP_DDR_BASE;
priv->info.size = 0;
return stm32mp1_ddr_setup();

13
drivers/st/gpio/stm32_gpio.c
View File

@ -15,8 +15,7 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_clkfunc.h>
#include <drivers/st/stm32mp_clkfunc.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
@ -208,7 +207,7 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
assert(pin <= GPIO_PIN_MAX);
stm32mp1_clk_enable(clock);
stm32mp_clk_enable(clock);
mmio_clrbits_32(base + GPIO_MODE_OFFSET,
((uint32_t)GPIO_MODE_MASK << (pin << 1)));
@ -254,17 +253,17 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
mmio_read_32(base + GPIO_AFRH_OFFSET));
stm32mp1_clk_disable((unsigned long)clock);
stm32mp_clk_disable(clock);
}
void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
{
uintptr_t base = stm32_get_gpio_bank_base(bank);
int clock = stm32_get_gpio_bank_clock(bank);
unsigned long clock = stm32_get_gpio_bank_clock(bank);
assert(pin <= GPIO_PIN_MAX);
stm32mp1_clk_enable((unsigned long)clock);
stm32mp_clk_enable(clock);
if (secure) {
mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
@ -272,5 +271,5 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
}
stm32mp1_clk_disable((unsigned long)clock);
stm32mp_clk_disable(clock);
}

1367
drivers/st/i2c/stm32_i2c.c
View File

File diff suppressed because it is too large Load Diff

54
drivers/st/mmc/stm32_sdmmc2.c
View File

@ -19,11 +19,7 @@
#include <drivers/mmc.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32_sdmmc2.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <drivers/st/stm32mp1_reset.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
#include <drivers/st/stm32mp_reset.h>
#include <lib/mmio.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
@ -123,8 +119,8 @@
SDMMC_STAR_IDMATE | \
SDMMC_STAR_IDMABTC)
#define TIMEOUT_10_MS (plat_get_syscnt_freq2() / 100U)
#define TIMEOUT_1_S plat_get_syscnt_freq2()
#define TIMEOUT_US_10_MS 10000U
#define TIMEOUT_US_1_S 1000000U
#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
@ -159,7 +155,7 @@ static void stm32_sdmmc2_init(void)
uintptr_t base = sdmmc2_params.reg_base;
clock_div = div_round_up(sdmmc2_params.clk_rate,
STM32MP1_MMC_INIT_FREQ * 2);
STM32MP_MMC_INIT_FREQ * 2);
mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div |
sdmmc2_params.negedge |
@ -185,11 +181,12 @@ static int stm32_sdmmc2_stop_transfer(void)
static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
{
uint64_t timeout;
uint32_t flags_cmd, status;
uint32_t flags_data = 0;
int err = 0;
uintptr_t base = sdmmc2_params.reg_base;
unsigned int cmd_reg, arg_reg, start;
unsigned int cmd_reg, arg_reg;
if (cmd == NULL) {
return -EINVAL;
@ -272,10 +269,10 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
status = mmio_read_32(base + SDMMC_STAR);
start = get_timer(0);
timeout = timeout_init_us(TIMEOUT_US_10_MS);
while ((status & flags_cmd) == 0U) {
if (get_timer(start) > TIMEOUT_10_MS) {
if (timeout_elapsed(timeout)) {
err = -ETIMEDOUT;
ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
__func__, cmd->cmd_idx, status);
@ -339,10 +336,10 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
status = mmio_read_32(base + SDMMC_STAR);
start = get_timer(0);
timeout = timeout_init_us(TIMEOUT_US_10_MS);
while ((status & flags_data) == 0U) {
if (get_timer(start) > TIMEOUT_10_MS) {
if (timeout_elapsed(timeout)) {
ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
__func__, cmd->cmd_idx, status);
err = -ETIMEDOUT;
@ -364,7 +361,7 @@ err_exit:
mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS);
if (err != 0) {
if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) {
int ret_stop = stm32_sdmmc2_stop_transfer();
if (ret_stop != 0) {
@ -429,15 +426,15 @@ static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width)
if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
if (max_bus_freq >= 52000000U) {
max_freq = STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ;
max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ;
} else {
max_freq = STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ;
max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ;
}
} else {
if (max_bus_freq >= 50000000U) {
max_freq = STM32MP1_SD_HIGH_SPEED_MAX_FREQ;
max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ;
} else {
max_freq = STM32MP1_SD_NORMAL_SPEED_MAX_FREQ;
max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ;
}
}
@ -523,7 +520,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
uint32_t *buffer;
uintptr_t base = sdmmc2_params.reg_base;
uintptr_t fifo_reg = base + SDMMC_FIFOR;
unsigned int start;
uint64_t timeout;
int ret;
/* Assert buf is 4 bytes aligned */
@ -541,7 +538,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
flags |= SDMMC_STAR_DBCKEND;
}
start = get_timer(0);
timeout = timeout_init_us(TIMEOUT_US_1_S);
do {
status = mmio_read_32(base + SDMMC_STAR);
@ -563,7 +560,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
return -EIO;
}
if (get_timer(start) > TIMEOUT_1_S) {
if (timeout_elapsed(timeout)) {
ERROR("%s: timeout 1s (status = %x)\n",
__func__, status);
mmio_write_32(base + SDMMC_ICR,
@ -705,8 +702,6 @@ unsigned long long stm32_sdmmc2_mmc_get_device_size(void)
int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
{
int ret;
assert((params != NULL) &&
((params->reg_base & MMC_BLOCK_MASK) == 0U) &&
((params->bus_width == MMC_BUS_WIDTH_1) ||
@ -720,19 +715,14 @@ int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
return -ENOMEM;
}
ret = stm32mp1_clk_enable(sdmmc2_params.clock_id);
if (ret != 0) {
ERROR("%s: clock %d failed\n", __func__,
sdmmc2_params.clock_id);
return ret;
}
stm32mp_clk_enable(sdmmc2_params.clock_id);
stm32mp1_reset_assert(sdmmc2_params.reset_id);
stm32mp_reset_assert(sdmmc2_params.reset_id);
udelay(2);
stm32mp1_reset_deassert(sdmmc2_params.reset_id);
stm32mp_reset_deassert(sdmmc2_params.reset_id);
mdelay(1);
sdmmc2_params.clk_rate = stm32mp1_clk_get_rate(sdmmc2_params.clock_id);
sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id);
return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate,
sdmmc2_params.bus_width, sdmmc2_params.flags,

155
drivers/st/pmic/stm32mp_pmic.c
View File

@ -5,7 +5,6 @@
*/
#include <errno.h>
#include <stdbool.h>
#include <libfdt.h>
@ -13,20 +12,12 @@
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32_i2c.h>
#include <drivers/st/stm32mp_pmic.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stpmic1.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
/* I2C Timing hard-coded value, for I2C clock source is HSI at 64MHz */
#define I2C_TIMING 0x10D07DB5
#define I2C_TIMEOUT 0xFFFFF
#define MASK_RESET_BUCK3 BIT(2)
#define STPMIC1_LDO12356_OUTPUT_MASK (uint8_t)(GENMASK(6, 2))
#define STPMIC1_LDO12356_OUTPUT_SHIFT 2
#define STPMIC1_LDO3_MODE (uint8_t)(BIT(7))
@ -46,25 +37,29 @@ static int dt_get_pmic_node(void *fdt)
return fdt_node_offset_by_compatible(fdt, -1, "st,stpmic1");
}
bool dt_check_pmic(void)
int dt_pmic_status(void)
{
int node;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return false;
return -ENOENT;
}
node = dt_get_pmic_node(fdt);
if (node < 0) {
VERBOSE("%s: No PMIC node found in DT\n", __func__);
return false;
if (node <= 0) {
return -FDT_ERR_NOTFOUND;
}
return fdt_get_status(node);
}
static int dt_pmic_i2c_config(struct dt_node_info *i2c_info)
/*
* Get PMIC and its I2C bus configuration from the device tree.
* Return 0 on success, negative on error, 1 if no PMIC node is found.
*/
static int dt_pmic_i2c_config(struct dt_node_info *i2c_info,
struct stm32_i2c_init_s *init)
{
int pmic_node, i2c_node;
void *fdt;
@ -76,7 +71,7 @@ static int dt_pmic_i2c_config(struct dt_node_info *i2c_info)
pmic_node = dt_get_pmic_node(fdt);
if (pmic_node < 0) {
return -FDT_ERR_NOTFOUND;
return 1;
}
cuint = fdt_getprop(fdt, pmic_node, "reg", NULL);
@ -99,10 +94,10 @@ static int dt_pmic_i2c_config(struct dt_node_info *i2c_info)
return -FDT_ERR_NOTFOUND;
}
return dt_set_pinctrl_config(i2c_node);
return stm32_i2c_get_setup_from_fdt(fdt, i2c_node, init);
}
int dt_pmic_enable_boot_on_regulators(void)
int dt_pmic_configure_boot_on_regulators(void)
{
int pmic_node, regulators_node, regulator_node;
void *fdt;
@ -120,14 +115,40 @@ int dt_pmic_enable_boot_on_regulators(void)
fdt_for_each_subnode(regulator_node, fdt, regulators_node) {
const fdt32_t *cuint;
const char *node_name;
const char *node_name = fdt_get_name(fdt, regulator_node, NULL);
uint16_t voltage;
int status;
#if defined(IMAGE_BL2)
if ((fdt_getprop(fdt, regulator_node, "regulator-boot-on",
NULL) == NULL) &&
(fdt_getprop(fdt, regulator_node, "regulator-always-on",
NULL) == NULL)) {
#else
if (fdt_getprop(fdt, regulator_node, "regulator-boot-on",
NULL) == NULL) {
#endif
continue;
}
if (fdt_getprop(fdt, regulator_node, "regulator-pull-down",
NULL) != NULL) {
status = stpmic1_regulator_pull_down_set(node_name);
if (status != 0) {
return status;
}
}
if (fdt_getprop(fdt, regulator_node, "st,mask-reset",
NULL) != NULL) {
status = stpmic1_regulator_mask_reset_set(node_name);
if (status != 0) {
return status;
}
}
cuint = fdt_getprop(fdt, regulator_node,
"regulator-min-microvolt", NULL);
if (cuint == NULL) {
@ -136,17 +157,13 @@ int dt_pmic_enable_boot_on_regulators(void)
/* DT uses microvolts, whereas driver awaits millivolts */
voltage = (uint16_t)(fdt32_to_cpu(*cuint) / 1000U);
node_name = fdt_get_name(fdt, regulator_node, NULL);
status = stpmic1_regulator_voltage_set(node_name, voltage);
if (status != 0) {
return status;
}
if (stpmic1_is_regulator_enabled(node_name) == 0U) {
int status;
status = stpmic1_regulator_voltage_set(node_name,
voltage);
if (status != 0) {
return status;
}
status = stpmic1_regulator_enable(node_name);
if (status != 0) {
return status;
@ -157,77 +174,77 @@ int dt_pmic_enable_boot_on_regulators(void)
return 0;
}
void initialize_pmic_i2c(void)
bool initialize_pmic_i2c(void)
{
int ret;
struct dt_node_info i2c_info;
struct i2c_handle_s *i2c = &i2c_handle;
struct stm32_i2c_init_s i2c_init;
if (dt_pmic_i2c_config(&i2c_info) != 0) {
ERROR("I2C configuration failed\n");
ret = dt_pmic_i2c_config(&i2c_info, &i2c_init);
if (ret < 0) {
ERROR("I2C configuration failed %d\n", ret);
panic();
}
if (stm32mp1_clk_enable((uint32_t)i2c_info.clock) < 0) {
ERROR("I2C clock enable failed\n");
panic();
if (ret != 0) {
return false;
}
/* Initialize PMIC I2C */
i2c_handle.i2c_base_addr = i2c_info.base;
i2c_handle.i2c_init.timing = I2C_TIMING;
i2c_handle.i2c_init.own_address1 = pmic_i2c_addr;
i2c_handle.i2c_init.addressing_mode = I2C_ADDRESSINGMODE_7BIT;
i2c_handle.i2c_init.dual_address_mode = I2C_DUALADDRESS_DISABLE;
i2c_handle.i2c_init.own_address2 = 0;
i2c_handle.i2c_init.own_address2_masks = I2C_OAR2_OA2NOMASK;
i2c_handle.i2c_init.general_call_mode = I2C_GENERALCALL_DISABLE;
i2c_handle.i2c_init.no_stretch_mode = I2C_NOSTRETCH_DISABLE;
i2c->i2c_base_addr = i2c_info.base;
i2c->dt_status = i2c_info.status;
i2c->clock = i2c_info.clock;
i2c_init.own_address1 = pmic_i2c_addr;
i2c_init.addressing_mode = I2C_ADDRESSINGMODE_7BIT;
i2c_init.dual_address_mode = I2C_DUALADDRESS_DISABLE;
i2c_init.own_address2 = 0;
i2c_init.own_address2_masks = I2C_OAR2_OA2NOMASK;
i2c_init.general_call_mode = I2C_GENERALCALL_DISABLE;
i2c_init.no_stretch_mode = I2C_NOSTRETCH_DISABLE;
i2c_init.analog_filter = 1;
i2c_init.digital_filter_coef = 0;
ret = stm32_i2c_init(&i2c_handle);
ret = stm32_i2c_init(i2c, &i2c_init);
if (ret != 0) {
ERROR("Cannot initialize I2C %x (%d)\n",
i2c_handle.i2c_base_addr, ret);
i2c->i2c_base_addr, ret);
panic();
}
ret = stm32_i2c_config_analog_filter(&i2c_handle,
I2C_ANALOGFILTER_ENABLE);
if (ret != 0) {
ERROR("Cannot initialize I2C analog filter (%d)\n", ret);
if (!stm32_i2c_is_device_ready(i2c, pmic_i2c_addr, 1,
I2C_TIMEOUT_BUSY_MS)) {
ERROR("I2C device not ready\n");
panic();
}
ret = stm32_i2c_is_device_ready(&i2c_handle, (uint16_t)pmic_i2c_addr, 1,
I2C_TIMEOUT);
if (ret != 0) {
ERROR("I2C device not ready (%d)\n", ret);
panic();
}
stpmic1_bind_i2c(i2c, (uint16_t)pmic_i2c_addr);
stpmic1_bind_i2c(&i2c_handle, (uint16_t)pmic_i2c_addr);
return true;
}
void initialize_pmic(void)
{
int status;
uint8_t read_val;
unsigned long pmic_version;
initialize_pmic_i2c();
if (!initialize_pmic_i2c()) {
VERBOSE("No PMIC\n");
return;
}
status = stpmic1_register_read(VERSION_STATUS_REG, &read_val);
if (status != 0) {
if (stpmic1_get_version(&pmic_version) != 0) {
ERROR("Failed to access PMIC\n");
panic();
}
INFO("PMIC version = 0x%x\n", read_val);
INFO("PMIC version = 0x%02lx\n", pmic_version);
stpmic1_dump_regulators();
/* Keep VDD on during the reset cycle */
status = stpmic1_register_update(MASK_RESET_BUCK_REG,
MASK_RESET_BUCK3,
MASK_RESET_BUCK3);
if (status != 0) {
#if defined(IMAGE_BL2)
if (dt_pmic_configure_boot_on_regulators() != 0) {
panic();
}
};
#endif
}
int pmic_ddr_power_init(enum ddr_type ddr_type)

11
drivers/st/pmic/stpmic1.c
View File

@ -8,7 +8,8 @@
#include <common/debug.h>
#include <drivers/st/stpmic1.h>
#include <plat/common/platform.h>
#define I2C_TIMEOUT_MS 25
struct regul_struct {
const char *dt_node_name;
@ -677,8 +678,9 @@ int stpmic1_regulator_voltage_get(const char *name)
int stpmic1_register_read(uint8_t register_id, uint8_t *value)
{
return stm32_i2c_mem_read(pmic_i2c_handle, pmic_i2c_addr,
(uint16_t)register_id, I2C_MEMADD_SIZE_8BIT,
value, 1, 100000);
(uint16_t)register_id,
I2C_MEMADD_SIZE_8BIT, value,
1, I2C_TIMEOUT_MS);
}
int stpmic1_register_write(uint8_t register_id, uint8_t value)
@ -687,7 +689,8 @@ int stpmic1_register_write(uint8_t register_id, uint8_t value)
status = stm32_i2c_mem_write(pmic_i2c_handle, pmic_i2c_addr,
(uint16_t)register_id,
I2C_MEMADD_SIZE_8BIT, &value, 1, 100000);
I2C_MEMADD_SIZE_8BIT, &value,
1, I2C_TIMEOUT_MS);
#if ENABLE_ASSERTIONS
if (status != 0) {

55
drivers/st/reset/stm32mp1_reset.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, STMicroelectronics - All Rights Reserved
* Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,32 +10,53 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <drivers/st/stm32mp1_reset.h>
#include <drivers/delay_timer.h>
#include <drivers/st/stm32mp_reset.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
#define RST_CLR_OFFSET 4U
#define RESET_TIMEOUT_US_1MS U(1000)
void stm32mp1_reset_assert(uint32_t id)
static uint32_t id2reg_offset(unsigned int reset_id)
{
uint32_t offset = (id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t);
uint32_t bit = id % (uint32_t)__LONG_BIT;
return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t);
}
mmio_write_32(RCC_BASE + offset, BIT(bit));
while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) == 0U) {
;
static uint8_t id2reg_bit_pos(unsigned int reset_id)
{
return (uint8_t)(reset_id & GENMASK(4, 0));
}
void stm32mp_reset_assert(uint32_t id)
{
uint32_t offset = id2reg_offset(id);
uint32_t bitmsk = BIT(id2reg_bit_pos(id));
uint64_t timeout_ref;
uintptr_t rcc_base = stm32mp_rcc_base();
mmio_write_32(rcc_base + offset, bitmsk);
timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS);
while ((mmio_read_32(rcc_base + offset) & bitmsk) == 0U) {
if (timeout_elapsed(timeout_ref)) {
panic();
}
}
}
void stm32mp1_reset_deassert(uint32_t id)
void stm32mp_reset_deassert(uint32_t id)
{
uint32_t offset = ((id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t)) +
RST_CLR_OFFSET;
uint32_t bit = id % (uint32_t)__LONG_BIT;
uint32_t offset = id2reg_offset(id) + RCC_RSTCLRR_OFFSET;
uint32_t bitmsk = BIT(id2reg_bit_pos(id));
uint64_t timeout_ref;
uintptr_t rcc_base = stm32mp_rcc_base();
mmio_write_32(RCC_BASE + offset, BIT(bit));
while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) != 0U) {
;
mmio_write_32(rcc_base + offset, bitmsk);
timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS);
while ((mmio_read_32(rcc_base + offset) & bitmsk) != 0U) {
if (timeout_elapsed(timeout_ref)) {
panic();
}
}
}

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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
/* STM32MP157C DK1/DK2 BOARD configuration
* 1x DDR3L 4Gb, 16-bit, 533MHz.
* Reference used NT5CC256M16DP-DI from NANYA
*
* DDR type / Platform DDR3/3L
* freq 533MHz
* width 16
* datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
* DDR density 4
* timing mode optimized
* Scheduling/QoS options : type = 2
* address mapping : RBC
* Tc > + 85C : N
*/
#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.41"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
#define DDR_MSTR 0x00041401
#define DDR_MRCTRL0 0x00000010
#define DDR_MRCTRL1 0x00000000
#define DDR_DERATEEN 0x00000000
#define DDR_DERATEINT 0x00800000
#define DDR_PWRCTL 0x00000000
#define DDR_PWRTMG 0x00400010
#define DDR_HWLPCTL 0x00000000
#define DDR_RFSHCTL0 0x00210000
#define DDR_RFSHCTL3 0x00000000
#define DDR_RFSHTMG 0x0081008B
#define DDR_CRCPARCTL0 0x00000000
#define DDR_DRAMTMG0 0x121B2414
#define DDR_DRAMTMG1 0x000A041C
#define DDR_DRAMTMG2 0x0608090F
#define DDR_DRAMTMG3 0x0050400C
#define DDR_DRAMTMG4 0x08040608
#define DDR_DRAMTMG5 0x06060403
#define DDR_DRAMTMG6 0x02020002
#define DDR_DRAMTMG7 0x00000202
#define DDR_DRAMTMG8 0x00001005
#define DDR_DRAMTMG14 0x000000A0
#define DDR_ZQCTL0 0xC2000040
#define DDR_DFITMG0 0x02060105
#define DDR_DFITMG1 0x00000202
#define DDR_DFILPCFG0 0x07000000
#define DDR_DFIUPD0 0xC0400003
#define DDR_DFIUPD1 0x00000000
#define DDR_DFIUPD2 0x00000000
#define DDR_DFIPHYMSTR 0x00000000
#define DDR_ADDRMAP1 0x00070707
#define DDR_ADDRMAP2 0x00000000
#define DDR_ADDRMAP3 0x1F000000
#define DDR_ADDRMAP4 0x00001F1F
#define DDR_ADDRMAP5 0x06060606
#define DDR_ADDRMAP6 0x0F060606
#define DDR_ADDRMAP9 0x00000000
#define DDR_ADDRMAP10 0x00000000
#define DDR_ADDRMAP11 0x00000000
#define DDR_ODTCFG 0x06000600
#define DDR_ODTMAP 0x00000001
#define DDR_SCHED 0x00000C01
#define DDR_SCHED1 0x00000000
#define DDR_PERFHPR1 0x01000001
#define DDR_PERFLPR1 0x08000200
#define DDR_PERFWR1 0x08000400
#define DDR_DBG0 0x00000000
#define DDR_DBG1 0x00000000
#define DDR_DBGCMD 0x00000000
#define DDR_POISONCFG 0x00000000
#define DDR_PCCFG 0x00000010
#define DDR_PCFGR_0 0x00010000
#define DDR_PCFGW_0 0x00000000
#define DDR_PCFGQOS0_0 0x02100C03
#define DDR_PCFGQOS1_0 0x00800100
#define DDR_PCFGWQOS0_0 0x01100C03
#define DDR_PCFGWQOS1_0 0x01000200
#define DDR_PCFGR_1 0x00010000
#define DDR_PCFGW_1 0x00000000
#define DDR_PCFGQOS0_1 0x02100C03
#define DDR_PCFGQOS1_1 0x00800040
#define DDR_PCFGWQOS0_1 0x01100C03
#define DDR_PCFGWQOS1_1 0x01000200
#define DDR_PGCR 0x01442E02
#define DDR_PTR0 0x0022AA5B
#define DDR_PTR1 0x04841104
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
#define DDR_DSGCR 0xF200001F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8
#define DDR_DTPR2 0x10023600
#define DDR_MR0 0x00000840
#define DDR_MR1 0x00000000
#define DDR_MR2 0x00000208
#define DDR_MR3 0x00000000
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2018-2019 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>.
*/
/dts-v1/;
#include "stm32mp157c.dtsi"
#include "stm32mp157cac-pinctrl.dtsi"
/ {
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
aliases {
serial0 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&clk_hse {
st,digbypass;
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
pmic: stpmic@33 {
compatible = "st,stpmic1";
reg = <0x33>;
interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
st,main-control-register = <0x04>;
st,vin-control-register = <0xc0>;
st,usb-control-register = <0x20>;
regulators {
compatible = "st,stpmic1-regulators";
ldo1-supply = <&v3v3>;
ldo3-supply = <&vdd_ddr>;
ldo6-supply = <&v3v3>;
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd_ddr: buck2 {
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
vdd: buck3 {
regulator-name = "vdd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
st,mask-reset;
regulator-initial-mode = <0>;
regulator-over-current-protection;
};
v3v3: buck4 {
regulator-name = "v3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-over-current-protection;
regulator-initial-mode = <0>;
};
v1v8_audio: ldo1 {
regulator-name = "v1v8_audio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
v3v3_hdmi: ldo2 {
regulator-name = "v3v3_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vtt_ddr: ldo3 {
regulator-name = "vtt_ddr";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <750000>;
regulator-always-on;
regulator-over-current-protection;
};
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdda: ldo5 {
regulator-name = "vdda";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
regulator-boot-on;
};
v1v2_hdmi: ldo6 {
regulator-name = "v1v2_hdmi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
regulator-over-current-protection;
};
};
};
};
&iwdg2 {
timeout-sec = <32>;
status = "okay";
};
&rng1 {
status = "okay";
};
&rtc {
status = "okay";
};
&sdmmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_b4_pins_a>;
broken-cd;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&v3v3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
status = "okay";
};
/* ATF Specific */
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
/ {
aliases {
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio25 = &gpioz;
i2c3 = &i2c4;
};
soc {
stgen: stgen@5C008000 {
compatible = "st,stm32-stgen";
reg = <0x5C008000 0x1000>;
status = "okay";
};
};
};
/* CLOCK init */
&rcc {
secure-status = "disabled";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_DISABLED
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4Q
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_LSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
};
};

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@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>.
*/
/dts-v1/;
#include "stm32mp157a-dk1.dts"
/ {
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
};

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fdts/stm32mp157c-ed1.dts
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@ -55,7 +55,7 @@
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <800000>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;

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fdts/stm32mp157cac-pinctrl.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com>
*/
#include "stm32mp157-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller@50002000 {
st,package = <STM32MP157CAC>;
gpioa: gpio@50002000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@50003000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@50004000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@50005000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@50006000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@50007000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@50008000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@50009000 {
status = "okay";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@5000a000 {
status = "okay";
ngpios = <12>;
gpio-ranges = <&pinctrl 0 128 12>;
};
};
pinctrl_z: pin-controller-z@54004000 {
st,package = <STM32MP157CAC>;
gpioz: gpio@54004000 {
status = "okay";
ngpios = <8>;
gpio-ranges = <&pinctrl_z 0 400 8>;
};
};
};
};

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include/drivers/st/stm32_i2c.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
* Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -111,94 +111,113 @@
#define I2C_ICR_TIMOUTCF BIT(12)
#define I2C_ICR_ALERTCF BIT(13)
enum i2c_speed_e {
I2C_SPEED_STANDARD, /* 100 kHz */
I2C_SPEED_FAST, /* 400 kHz */
I2C_SPEED_FAST_PLUS, /* 1 MHz */
};
#define STANDARD_RATE 100000
#define FAST_RATE 400000
#define FAST_PLUS_RATE 1000000
struct stm32_i2c_init_s {
uint32_t timing; /* Specifies the I2C_TIMINGR_register value
* This parameter is calculated by referring
* to I2C initialization section in Reference
* manual.
*/
uint32_t own_address1; /*
* Specifies the first device own
* address. This parameter can be a
* 7-bit or 10-bit address.
*/
uint32_t own_address1; /* Specifies the first device own address.
* This parameter can be a 7-bit or 10-bit
* address.
*/
uint32_t addressing_mode; /*
* Specifies if 7-bit or 10-bit
* addressing mode is selected.
* This parameter can be a value of
* @ref I2C_ADDRESSING_MODE.
*/
uint32_t addressing_mode; /* Specifies if 7-bit or 10-bit addressing
* mode is selected.
* This parameter can be a value of @ref
* I2C_ADDRESSING_MODE.
*/
uint32_t dual_address_mode; /*
* Specifies if dual addressing mode is
* selected.
* This parameter can be a value of @ref
* I2C_DUAL_ADDRESSING_MODE.
*/
uint32_t dual_address_mode; /* Specifies if dual addressing mode is
* selected.
* This parameter can be a value of @ref
* I2C_DUAL_ADDRESSING_MODE.
*/
uint32_t own_address2; /*
* Specifies the second device own
* address if dual addressing mode is
* selected. This parameter can be a
* 7-bit address.
*/
uint32_t own_address2; /* Specifies the second device own address
* if dual addressing mode is selected.
* This parameter can be a 7-bit address.
*/
uint32_t own_address2_masks; /*
* Specifies the acknowledge mask
* address second device own address
* if dual addressing mode is selected
* This parameter can be a value of @ref
* I2C_OWN_ADDRESS2_MASKS.
*/
uint32_t own_address2_masks; /* Specifies the acknowledge mask address
* second device own address if dual
* addressing mode is selected.
* This parameter can be a value of @ref
* I2C_OWN_ADDRESS2_MASKS.
*/
uint32_t general_call_mode; /*
* Specifies if general call mode is
* selected.
* This parameter can be a value of @ref
* I2C_GENERAL_CALL_ADDRESSING_MODE.
*/
uint32_t general_call_mode; /* Specifies if general call mode is
* selected.
* This parameter can be a value of @ref
* I2C_GENERAL_CALL_ADDRESSING_MODE.
*/
uint32_t no_stretch_mode; /*
* Specifies if nostretch mode is
* selected.
* This parameter can be a value of @ref
* I2C_NOSTRETCH_MODE.
*/
uint32_t no_stretch_mode; /* Specifies if nostretch mode is
* selected.
* This parameter can be a value of @ref
* I2C_NOSTRETCH_MODE.
*/
uint32_t rise_time; /*
* Specifies the SCL clock pin rising
* time in nanoseconds.
*/
uint32_t fall_time; /*
* Specifies the SCL clock pin falling
* time in nanoseconds.
*/
enum i2c_speed_e speed_mode; /*
* Specifies the I2C clock source
* frequency mode.
* This parameter can be a value of @ref
* i2c_speed_mode_e.
*/
int analog_filter; /*
* Specifies if the I2C analog noise
* filter is selected.
* This parameter can be 0 (filter
* off), all other values mean filter
* on.
*/
uint8_t digital_filter_coef; /*
* Specifies the I2C digital noise
* filter coefficient.
* This parameter can be a value
* between 0 and
* STM32_I2C_DIGITAL_FILTER_MAX.
*/
};
enum i2c_state_e {
I2C_STATE_RESET = 0x00U, /* Peripheral is not yet
* initialized.
*/
I2C_STATE_READY = 0x20U, /* Peripheral Initialized
* and ready for use.
*/
I2C_STATE_BUSY = 0x24U, /* An internal process is
* ongoing.
*/
I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission process
* is ongoing.
*/
I2C_STATE_BUSY_RX = 0x22U, /* Data Reception process
* is ongoing.
*/
I2C_STATE_LISTEN = 0x28U, /* Address Listen Mode is
* ongoing.
*/
I2C_STATE_BUSY_TX_LISTEN = 0x29U, /* Address Listen Mode
* and Data Transmission
* process is ongoing.
*/
I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /* Address Listen Mode
* and Data Reception
* process is ongoing.
*/
I2C_STATE_ABORT = 0x60U, /* Abort user request ongoing. */
I2C_STATE_TIMEOUT = 0xA0U, /* Timeout state. */
I2C_STATE_ERROR = 0xE0U /* Error. */
I2C_STATE_RESET = 0x00U, /* Not yet initialized */
I2C_STATE_READY = 0x20U, /* Ready for use */
I2C_STATE_BUSY = 0x24U, /* Internal process ongoing */
I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission ongoing */
I2C_STATE_BUSY_RX = 0x22U, /* Data Reception ongoing */
};
enum i2c_mode_e {
I2C_MODE_NONE = 0x00U, /* No I2C communication on going. */
I2C_MODE_MASTER = 0x10U, /* I2C communication is in Master Mode. */
I2C_MODE_SLAVE = 0x20U, /* I2C communication is in Slave Mode. */
I2C_MODE_MEM = 0x40U /* I2C communication is in Memory Mode. */
I2C_MODE_NONE = 0x00U, /* No active communication */
I2C_MODE_MASTER = 0x10U, /* Communication in Master Mode */
I2C_MODE_SLAVE = 0x20U, /* Communication in Slave Mode */
I2C_MODE_MEM = 0x40U /* Communication in Memory Mode */
};
@ -213,26 +232,12 @@ enum i2c_mode_e {
struct i2c_handle_s {
uint32_t i2c_base_addr; /* Registers base address */
struct stm32_i2c_init_s i2c_init; /* Communication parameters */
uint8_t *p_buff; /* Pointer to transfer buffer */
uint16_t xfer_size; /* Transfer size */
uint16_t xfer_count; /* Transfer counter */
uint32_t prev_state; /* Communication previous
* state
*/
uint8_t lock; /* Locking object */
enum i2c_state_e i2c_state; /* Communication state */
enum i2c_mode_e i2c_mode; /* Communication mode */
uint32_t i2c_err; /* Error code */
unsigned int dt_status; /* DT nsec/sec status */
unsigned int clock; /* Clock reference */
uint8_t lock; /* Locking object */
enum i2c_state_e i2c_state; /* Communication state */
enum i2c_mode_e i2c_mode; /* Communication mode */
uint32_t i2c_err; /* Error code */
};
#define I2C_ADDRESSINGMODE_7BIT 0x00000001U
@ -250,15 +255,15 @@ struct i2c_handle_s {
#define I2C_MEMADD_SIZE_8BIT 0x00000001U
#define I2C_MEMADD_SIZE_16BIT 0x00000002U
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE 0x00000000U
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE 0x00000000U
#define I2C_NO_STARTSTOP 0x00000000U
#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \
#define I2C_NO_STARTSTOP 0x00000000U
#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \
I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START)
#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START)
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
@ -281,21 +286,36 @@ struct i2c_handle_s {
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
#define I2C_TIMEOUT_BUSY_MS 25U
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
int stm32_i2c_init(struct i2c_handle_s *hi2c);
/* STM32 specific defines */
#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */
#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */
#define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD
#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
#define STM32_I2C_DIGITAL_FILTER_MAX 16
int stm32_i2c_get_setup_from_fdt(void *fdt, int node,
struct stm32_i2c_init_s *init);
int stm32_i2c_init(struct i2c_handle_s *hi2c,
struct stm32_i2c_init_s *init_data);
int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout);
uint8_t *p_data, uint16_t size, uint32_t timeout_ms);
int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint16_t mem_addr, uint16_t mem_add_size,
uint8_t *p_data, uint16_t size, uint32_t timeout);
int stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint32_t trials, uint32_t timeout);
int stm32_i2c_config_analog_filter(struct i2c_handle_s *hi2c,
uint32_t analog_filter);
uint8_t *p_data, uint16_t size, uint32_t timeout_ms);
int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint8_t *p_data, uint16_t size,
uint32_t timeout_ms);
int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint8_t *p_data, uint16_t size,
uint32_t timeout_ms);
bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr,
uint32_t trials, uint32_t timeout_ms);
#endif /* STM32_I2C_H */

45
include/drivers/st/stm32mp1_clk.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, STMicroelectronics - All Rights Reserved
* Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,25 +7,42 @@
#ifndef STM32MP1_CLK_H
#define STM32MP1_CLK_H
#include <stdbool.h>
#include <arch_helpers.h>
int stm32mp1_clk_probe(void);
int stm32mp1_clk_init(void);
bool stm32mp1_clk_is_enabled(unsigned long id);
int stm32mp1_clk_enable(unsigned long id);
int stm32mp1_clk_disable(unsigned long id);
unsigned long stm32mp1_clk_get_rate(unsigned long id);
void stm32mp1_stgen_increment(unsigned long long offset_in_ms);
static inline uint32_t get_timer(uint32_t base)
bool stm32mp1_rcc_is_secure(void);
void __stm32mp1_clk_enable(unsigned long id, bool caller_is_secure);
void __stm32mp1_clk_disable(unsigned long id, bool caller_is_secure);
static inline void stm32mp1_clk_enable_non_secure(unsigned long id)
{
if (base == 0U) {
return (uint32_t)(~read_cntpct_el0());
}
return base - (uint32_t)(~read_cntpct_el0());
__stm32mp1_clk_enable(id, false);
}
static inline void stm32mp1_clk_enable_secure(unsigned long id)
{
__stm32mp1_clk_enable(id, true);
}
static inline void stm32mp1_clk_disable_non_secure(unsigned long id)
{
__stm32mp1_clk_disable(id, false);
}
static inline void stm32mp1_clk_disable_secure(unsigned long id)
{
__stm32mp1_clk_disable(id, true);
}
unsigned int stm32mp1_clk_get_refcount(unsigned long id);
/* SMP protection on RCC registers access */
void stm32mp1_clk_rcc_regs_lock(void);
void stm32mp1_clk_rcc_regs_unlock(void);
void stm32mp1_stgen_increment(unsigned long long offset_in_ms);
#endif /* STM32MP1_CLK_H */

13
include/drivers/st/stm32mp1_clkfunc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -18,7 +18,6 @@ enum stm32mp_osc_id {
_LSI,
_LSE,
_I2S_CKIN,
_USB_PHY_48,
NB_OSC,
_UNKNOWN_OSC_ID = 0xFF
};
@ -31,14 +30,4 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
const char *prop_name,
uint32_t dflt_value);
uint32_t fdt_rcc_read_addr(void);
int fdt_rcc_read_uint32_array(const char *prop_name,
uint32_t *array, uint32_t count);
int fdt_rcc_subnode_offset(const char *name);
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
bool fdt_get_rcc_secure_status(void);
uintptr_t fdt_get_stgen_base(void);
int fdt_get_clock_id(int node);
#endif /* STM32MP1_CLKFUNC_H */

3
include/drivers/st/stm32mp1_rcc.h
View File

@ -280,6 +280,9 @@
/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
#define RCC_MP_ENCLRR_OFFSET U(4)
/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */
#define RCC_RSTCLRR_OFFSET U(4)
/* Fields of RCC_BDCR register */
#define RCC_BDCR_LSEON BIT(0)
#define RCC_BDCR_LSEBYP BIT(1)

15
include/drivers/st/stm32mp1_reset.h
View File

@ -1,15 +0,0 @@
/*
* Copyright (c) 2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_RESET_H
#define STM32MP1_RESET_H
#include <stdint.h>
void stm32mp1_reset_assert(uint32_t reset_id);
void stm32mp1_reset_deassert(uint32_t reset_id);
#endif /* STM32MP1_RESET_H */

25
include/drivers/st/stm32mp_clkfunc.h Normal file
View File

@ -0,0 +1,25 @@
/*
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP_CLKFUNC_H
#define STM32MP_CLKFUNC_H
#include <stdbool.h>
#include <libfdt.h>
int fdt_get_rcc_node(void *fdt);
uint32_t fdt_rcc_read_addr(void);
int fdt_rcc_read_uint32_array(const char *prop_name,
uint32_t *array, uint32_t count);
int fdt_rcc_subnode_offset(const char *name);
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
bool fdt_get_rcc_secure_status(void);
uintptr_t fdt_get_stgen_base(void);
int fdt_get_clock_id(int node);
#endif /* STM32MP_CLKFUNC_H */

37
include/drivers/st/stm32mp_pmic.h
View File

@ -11,10 +11,41 @@
#include <platform_def.h>
bool dt_check_pmic(void);
int dt_pmic_enable_boot_on_regulators(void);
void initialize_pmic_i2c(void);
/*
* dt_pmic_status - Check PMIC status from device tree
*
* Returns the status of the PMIC (secure, non-secure), or a negative value on
* error
*/
int dt_pmic_status(void);
/*
* dt_pmic_configure_boot_on_regulators - Configure boot-on and always-on
* regulators from device tree configuration
*
* Returns 0 on success, and negative values on errors
*/
int dt_pmic_configure_boot_on_regulators(void);
/*
* initialize_pmic_i2c - Initialize I2C for the PMIC control
*
* Returns true if PMIC is available, false if not found, panics on errors
*/
bool initialize_pmic_i2c(void);
/*
* initialize_pmic - Main PMIC initialization function, called at platform init
*
* Panics on errors
*/
void initialize_pmic(void);
/*
* pmic_ddr_power_init - Initialize regulators required for DDR
*
* Returns 0 on success, and negative values on errors
*/
int pmic_ddr_power_init(enum ddr_type ddr_type);
#endif /* STM32MP_PMIC_H */

15
include/drivers/st/stm32mp_reset.h Normal file
View File

@ -0,0 +1,15 @@
/*
* Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP_RESET_H
#define STM32MP_RESET_H
#include <stdint.h>
void stm32mp_reset_assert(uint32_t reset_id);
void stm32mp_reset_deassert(uint32_t reset_id);
#endif /* STM32MP_RESET_H */

22
plat/st/stm32mp1/bl2_io_storage.c → plat/st/common/bl2_io_storage.c
View File

@ -20,14 +20,10 @@
#include <drivers/st/io_mmc.h>
#include <drivers/st/io_stm32image.h>
#include <drivers/st/stm32_sdmmc2.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <lib/mmio.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
#include <boot_api.h>
#include <stm32mp1_private.h>
/* IO devices */
static const io_dev_connector_t *dummy_dev_con;
static uintptr_t dummy_dev_handle;
@ -60,12 +56,12 @@ static const io_dev_connector_t *mmc_dev_con;
static const io_block_spec_t bl32_block_spec = {
.offset = BL32_BASE,
.length = STM32MP1_BL32_SIZE
.length = STM32MP_BL32_SIZE
};
static const io_block_spec_t bl2_block_spec = {
.offset = BL2_BASE,
.length = STM32MP1_BL2_SIZE,
.length = STM32MP_BL2_SIZE,
};
static const struct stm32image_part_info bl33_partition_spec = {
@ -166,7 +162,7 @@ static void print_boot_device(boot_api_context_t *boot_context)
}
}
void stm32mp1_io_setup(void)
void stm32mp_io_setup(void)
{
int io_result __unused;
uint8_t idx;
@ -176,7 +172,7 @@ void stm32mp1_io_setup(void)
uintptr_t mmc_default_instance;
const partition_entry_t *entry;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
print_boot_device(boot_context);
@ -203,21 +199,21 @@ void stm32mp1_io_setup(void)
if (boot_context->boot_interface_selected ==
BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC) {
device_info.mmc_dev_type = MMC_IS_EMMC;
mmc_default_instance = STM32MP1_SDMMC2_BASE;
mmc_default_instance = STM32MP_SDMMC2_BASE;
} else {
device_info.mmc_dev_type = MMC_IS_SD;
mmc_default_instance = STM32MP1_SDMMC1_BASE;
mmc_default_instance = STM32MP_SDMMC1_BASE;
}
switch (boot_context->boot_interface_instance) {
case 1:
params.reg_base = STM32MP1_SDMMC1_BASE;
params.reg_base = STM32MP_SDMMC1_BASE;
break;
case 2:
params.reg_base = STM32MP1_SDMMC2_BASE;
params.reg_base = STM32MP_SDMMC2_BASE;
break;
case 3:
params.reg_base = STM32MP1_SDMMC3_BASE;
params.reg_base = STM32MP_SDMMC3_BASE;
break;
default:
WARN("SDMMC instance not found, using default\n");

75
plat/st/common/include/stm32mp_common.h Normal file
View File

@ -0,0 +1,75 @@
/*
* Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2018-2019, Linaro Limited
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP_COMMON_H
#define STM32MP_COMMON_H
#include <stdbool.h>
#include <arch_helpers.h>
/* Functions to save and get boot context address given by ROM code */
void stm32mp_save_boot_ctx_address(uintptr_t address);
uintptr_t stm32mp_get_boot_ctx_address(void);
/* Return the base address of the DDR controller */
uintptr_t stm32mp_ddrctrl_base(void);
/* Return the base address of the DDR PHY */
uintptr_t stm32mp_ddrphyc_base(void);
/* Return the base address of the PWR peripheral */
uintptr_t stm32mp_pwr_base(void);
/* Return the base address of the RCC peripheral */
uintptr_t stm32mp_rcc_base(void);
/*
* Platform util functions for the GPIO driver
* @bank: Target GPIO bank ID as per DT bindings
*
* Platform shall implement these functions to provide to stm32_gpio
* driver the resource reference for a target GPIO bank. That are
* memory mapped interface base address, interface offset (see below)
* and clock identifier.
*
* stm32_get_gpio_bank_offset() returns a bank offset that is used to
* check DT configuration matches platform implementation of the banks
* description.
*/
uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
/*
* Util for clock gating and to get clock rate for stm32 and platform drivers
* @id: Target clock ID, ID used in clock DT bindings
*/
bool stm32mp_clk_is_enabled(unsigned long id);
void stm32mp_clk_enable(unsigned long id);
void stm32mp_clk_disable(unsigned long id);
unsigned long stm32mp_clk_get_rate(unsigned long id);
/* Initialise the IO layer and register platform IO devices */
void stm32mp_io_setup(void);
static inline uint64_t arm_cnt_us2cnt(uint32_t us)
{
return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL;
}
static inline uint64_t timeout_init_us(uint32_t us)
{
return read_cntpct_el0() + arm_cnt_us2cnt(us);
}
static inline bool timeout_elapsed(uint64_t expire)
{
return read_cntpct_el0() > expire;
}
#endif /* STM32MP_COMMON_H */

11
plat/st/stm32mp1/include/stm32mp1_dt.h → plat/st/common/include/stm32mp_dt.h
View File

@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_DT_H
#define STM32MP1_DT_H
#ifndef STM32MP_DT_H
#define STM32MP_DT_H
#include <stdbool.h>
@ -27,7 +27,7 @@ struct dt_node_info {
int dt_open_and_check(void);
int fdt_get_address(void **fdt_addr);
bool fdt_check_node(int node);
uint32_t fdt_get_status(int node);
uint8_t fdt_get_status(int node);
uint32_t fdt_read_uint32_default(int node, const char *prop_name,
uint32_t dflt_value);
int fdt_read_uint32_array(int node, const char *prop_name,
@ -38,6 +38,9 @@ int dt_get_node(struct dt_node_info *info, int offset, const char *compat);
int dt_get_stdout_uart_info(struct dt_node_info *info);
int dt_get_stdout_node_offset(void);
uint32_t dt_get_ddr_size(void);
uintptr_t dt_get_ddrctrl_base(void);
uintptr_t dt_get_ddrphyc_base(void);
uintptr_t dt_get_pwr_base(void);
const char *dt_get_board_model(void);
#endif /* STM32MP1_DT_H */
#endif /* STM32MP_DT_H */

74
plat/st/common/include/stm32mp_shres_helpers.h Normal file
View File

@ -0,0 +1,74 @@
/*
* Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP_SHRES_HELPERS_H
#define STM32MP_SHRES_HELPERS_H
#include <stdint.h>
#include <common/debug.h>
/*
* Shared reference counter: increments by 2 on secure increment
* request, decrements by 2 on secure decrement request. Bit #0
* is set to 1 on non-secure increment request and reset to 0 on
* non-secure decrement request. The counter initializes to
* either 0, 1 or 2 upon their expect default state.
* Counters saturates once above UINT_MAX / 2.
*/
#define SHREFCNT_NONSECURE_FLAG 0x1UL
#define SHREFCNT_SECURE_STEP 0x2UL
#define SHREFCNT_MAX (UINT32_MAX / 2)
/* Return 1 if refcnt increments from 0, else return 0 */
static inline int stm32mp_incr_shrefcnt(unsigned int *refcnt, bool secure)
{
int rc = !*refcnt;
if (secure) {
*refcnt += SHREFCNT_SECURE_STEP;
if (*refcnt >= SHREFCNT_MAX) {
panic();
}
} else {
*refcnt |= SHREFCNT_NONSECURE_FLAG;
}
return rc;
}
/* Return 1 if refcnt decrements to 0, else return 0 */
static inline int stm32mp_decr_shrefcnt(unsigned int *refcnt, bool secure)
{
int rc = 0;
if (secure) {
if (*refcnt < SHREFCNT_MAX) {
if (*refcnt < SHREFCNT_SECURE_STEP) {
panic();
}
*refcnt -= SHREFCNT_SECURE_STEP;
rc = !*refcnt;
}
} else {
rc = (*refcnt == SHREFCNT_NONSECURE_FLAG) ? 1 : 0;
*refcnt &= ~SHREFCNT_NONSECURE_FLAG;
}
return rc;
}
static inline int stm32mp_incr_refcnt(unsigned int *refcnt)
{
return stm32mp_incr_shrefcnt(refcnt, true);
}
static inline int stm32mp_decr_refcnt(unsigned int *refcnt)
{
return stm32mp_decr_shrefcnt(refcnt, true);
}
#endif /* STM32MP_SHRES_HELPERS_H */

121
plat/st/common/stm32mp_common.c Normal file
View File

@ -0,0 +1,121 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <platform_def.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/st/stm32mp_clkfunc.h>
#include <plat/common/platform.h>
uintptr_t plat_get_ns_image_entrypoint(void)
{
return BL33_BASE;
}
unsigned int plat_get_syscnt_freq2(void)
{
return read_cntfrq_el0();
}
static uintptr_t boot_ctx_address;
void stm32mp_save_boot_ctx_address(uintptr_t address)
{
boot_ctx_address = address;
}
uintptr_t stm32mp_get_boot_ctx_address(void)
{
return boot_ctx_address;
}
uintptr_t stm32mp_ddrctrl_base(void)
{
static uintptr_t ddrctrl_base;
if (ddrctrl_base == 0) {
ddrctrl_base = dt_get_ddrctrl_base();
assert(ddrctrl_base == DDRCTRL_BASE);
}
return ddrctrl_base;
}
uintptr_t stm32mp_ddrphyc_base(void)
{
static uintptr_t ddrphyc_base;
if (ddrphyc_base == 0) {
ddrphyc_base = dt_get_ddrphyc_base();
assert(ddrphyc_base == DDRPHYC_BASE);
}
return ddrphyc_base;
}
uintptr_t stm32mp_pwr_base(void)
{
static uintptr_t pwr_base;
if (pwr_base == 0) {
pwr_base = dt_get_pwr_base();
assert(pwr_base == PWR_BASE);
}
return pwr_base;
}
uintptr_t stm32mp_rcc_base(void)
{
static uintptr_t rcc_base;
if (rcc_base == 0) {
rcc_base = fdt_rcc_read_addr();
assert(rcc_base == RCC_BASE);
}
return rcc_base;
}
uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
{
if (bank == GPIO_BANK_Z) {
return GPIOZ_BASE;
}
assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
}
unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
{
if (bank == GPIO_BANK_Z) {
return GPIOZ;
}
assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
return GPIOA + (bank - GPIO_BANK_A);
}
uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
{
if (bank == GPIO_BANK_Z) {
return 0;
}
assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
return bank * GPIO_BANK_OFFSET;
}

77
plat/st/stm32mp1/stm32mp1_dt.c → plat/st/common/stm32mp_dt.c
View File

@ -13,14 +13,14 @@
#include <common/debug.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_clkfunc.h>
#include <drivers/st/stm32mp1_ddr.h>
#include <drivers/st/stm32mp1_ram.h>
#include <stm32mp_dt.h>
static int fdt_checked;
static void *fdt = (void *)(uintptr_t)STM32MP1_DTB_BASE;
static void *fdt = (void *)(uintptr_t)STM32MP_DTB_BASE;
/*******************************************************************************
* This function checks device tree file with its header.
@ -68,9 +68,9 @@ bool fdt_check_node(int node)
/*******************************************************************************
* This function return global node status (generic use of fdt library).
******************************************************************************/
uint32_t fdt_get_status(int node)
uint8_t fdt_get_status(int node)
{
uint32_t status = DT_DISABLED;
uint8_t status = DT_DISABLED;
int len;
const char *cchar;
@ -291,6 +291,73 @@ uint32_t dt_get_ddr_size(void)
return fdt_read_uint32_default(node, "st,mem-size", 0);
}
/*******************************************************************************
* This function gets DDRCTRL base address information from the DT.
* Returns value on success, and 0 on failure.
******************************************************************************/
uintptr_t dt_get_ddrctrl_base(void)
{
int node;
uint32_t array[4];
node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
if (node < 0) {
INFO("%s: Cannot read DDR node in DT\n", __func__);
return 0;
}
if (fdt_read_uint32_array(node, "reg", array, 4) < 0) {
return 0;
}
return array[0];
}
/*******************************************************************************
* This function gets DDRPHYC base address information from the DT.
* Returns value on success, and 0 on failure.
******************************************************************************/
uintptr_t dt_get_ddrphyc_base(void)
{
int node;
uint32_t array[4];
node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
if (node < 0) {
INFO("%s: Cannot read DDR node in DT\n", __func__);
return 0;
}
if (fdt_read_uint32_array(node, "reg", array, 4) < 0) {
return 0;
}
return array[2];
}
/*******************************************************************************
* This function gets PWR base address information from the DT.
* Returns value on success, and 0 on failure.
******************************************************************************/
uintptr_t dt_get_pwr_base(void)
{
int node;
const fdt32_t *cuint;
node = fdt_node_offset_by_compatible(fdt, -1, DT_PWR_COMPAT);
if (node < 0) {
INFO("%s: Cannot read PWR node in DT\n", __func__);
return 0;
}
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/*******************************************************************************
* This function retrieves board model from DT
* Returns string taken from model node, NULL otherwise

51
plat/st/stm32mp1/bl2_plat_setup.c
View File

@ -17,25 +17,21 @@
#include <drivers/generic_delay_timer.h>
#include <drivers/st/stm32_console.h>
#include <drivers/st/stm32mp_pmic.h>
#include <drivers/st/stm32mp_reset.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_pwr.h>
#include <drivers/st/stm32mp1_ram.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <drivers/st/stm32mp1_reset.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <boot_api.h>
#include <stm32mp1_context.h>
#include <stm32mp1_dt.h>
#include <stm32mp1_private.h>
static struct console_stm32 console;
static void print_reset_reason(void)
{
uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
if (rstsr == 0U) {
WARN("Reset reason unknown\n");
@ -123,14 +119,14 @@ void bl2_el3_early_platform_setup(u_register_t arg0,
u_register_t arg2 __unused,
u_register_t arg3 __unused)
{
stm32mp1_save_boot_ctx_address(arg0);
stm32mp_save_boot_ctx_address(arg0);
}
void bl2_platform_setup(void)
{
int ret;
if (dt_check_pmic()) {
if (dt_pmic_status() > 0) {
initialize_pmic();
}
@ -149,8 +145,10 @@ void bl2_el3_plat_arch_setup(void)
struct dt_node_info dt_uart_info;
const char *board_model;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
uint32_t clk_rate;
uintptr_t pwr_base;
uintptr_t rcc_base;
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
BL_CODE_END - BL_CODE_BASE,
@ -162,9 +160,9 @@ void bl2_el3_plat_arch_setup(void)
MT_MEMORY | MT_RO | MT_SECURE);
/* Map non secure DDR for BL33 load and DDR training area restore */
mmap_add_region(STM32MP1_DDR_BASE,
STM32MP1_DDR_BASE,
STM32MP1_DDR_MAX_SIZE,
mmap_add_region(STM32MP_DDR_BASE,
STM32MP_DDR_BASE,
STM32MP_DDR_MAX_SIZE,
MT_MEMORY | MT_RW | MT_NS);
/* Prevent corruption of preloaded Device Tree */
@ -178,27 +176,30 @@ void bl2_el3_plat_arch_setup(void)
panic();
}
pwr_base = stm32mp_pwr_base();
rcc_base = stm32mp_rcc_base();
/*
* Disable the backup domain write protection.
* The protection is enable at each reset by hardware
* and must be disabled by software.
*/
mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP);
mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) {
while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
;
}
/* Reset backup domain on cold boot cases */
if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) ==
while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
0U) {
;
}
mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
}
generic_delay_timer_init();
@ -224,19 +225,17 @@ void bl2_el3_plat_arch_setup(void)
goto skip_console_init;
}
if (stm32mp1_clk_enable((unsigned long)dt_uart_info.clock) != 0) {
goto skip_console_init;
}
stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
stm32mp1_reset_assert((uint32_t)dt_uart_info.reset);
stm32mp_reset_assert((uint32_t)dt_uart_info.reset);
udelay(2);
stm32mp1_reset_deassert((uint32_t)dt_uart_info.reset);
stm32mp_reset_deassert((uint32_t)dt_uart_info.reset);
mdelay(1);
clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_uart_info.clock);
clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
if (console_stm32_register(dt_uart_info.base, clk_rate,
STM32MP1_UART_BAUDRATE, &console) == 0) {
STM32MP_UART_BAUDRATE, &console) == 0) {
panic();
}
@ -257,5 +256,5 @@ skip_console_init:
print_reset_reason();
stm32mp1_io_setup();
stm32mp_io_setup();
}

26
plat/st/stm32mp1/include/platform_def.h
View File

@ -29,8 +29,8 @@
#define BL33_IMAGE_NAME "ssbl"
#define BL33_BINARY_TYPE U(0x0)
#define STM32MP1_PRIMARY_CPU U(0x0)
#define STM32MP1_SECONDARY_CPU U(0x1)
#define STM32MP_PRIMARY_CPU U(0x0)
#define STM32MP_SECONDARY_CPU U(0x1)
#define PLATFORM_CLUSTER_COUNT ULL(1)
#define PLATFORM_CLUSTER0_CORE_COUNT U(2)
@ -50,33 +50,33 @@
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
#define BL2_BASE STM32MP1_BL2_BASE
#define BL2_LIMIT (STM32MP1_BL2_BASE + \
STM32MP1_BL2_SIZE)
#define BL2_BASE STM32MP_BL2_BASE
#define BL2_LIMIT (STM32MP_BL2_BASE + \
STM32MP_BL2_SIZE)
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
#define BL32_BASE STM32MP1_BL32_BASE
#define BL32_LIMIT (STM32MP1_BL32_BASE + \
STM32MP1_BL32_SIZE)
#define BL32_BASE STM32MP_BL32_BASE
#define BL32_LIMIT (STM32MP_BL32_BASE + \
STM32MP_BL32_SIZE)
/*******************************************************************************
* BL33 specific defines.
******************************************************************************/
#define BL33_BASE STM32MP1_BL33_BASE
#define BL33_BASE STM32MP_BL33_BASE
/*
* Load address of BL33 for this platform port
*/
#define PLAT_STM32MP1_NS_IMAGE_OFFSET BL33_BASE
#define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE
/*******************************************************************************
* DTB specific defines.
******************************************************************************/
#define DTB_BASE STM32MP1_DTB_BASE
#define DTB_LIMIT (STM32MP1_DTB_BASE + \
STM32MP1_DTB_SIZE)
#define DTB_BASE STM32MP_DTB_BASE
#define DTB_LIMIT (STM32MP_DTB_BASE + \
STM32MP_DTB_SIZE)
/*******************************************************************************
* Platform specific page table and MMU setup constants

8
plat/st/stm32mp1/include/stm32mp1_private.h
View File

@ -9,20 +9,12 @@
#include <stdint.h>
void stm32mp1_io_setup(void);
void configure_mmu(void);
void stm32mp1_arch_security_setup(void);
void stm32mp1_security_setup(void);
void stm32mp1_save_boot_ctx_address(uintptr_t address);
uintptr_t stm32mp1_get_boot_ctx_address(void);
void stm32mp1_gic_pcpu_init(void);
void stm32mp1_gic_init(void);
uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
#endif /* STM32MP1_PRIVATE_H */

10
plat/st/stm32mp1/plat_bl2_mem_params_desc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -50,7 +50,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
VERSION_2, entry_point_info_t,
NON_SECURE | EXECUTABLE),
.ep_info.pc = PLAT_STM32MP1_NS_IMAGE_OFFSET,
.ep_info.pc = PLAT_STM32MP_NS_IMAGE_OFFSET,
.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
SPSR_E_LITTLE,
DISABLE_ALL_EXCEPTIONS),
@ -58,9 +58,9 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
.image_info.image_base = PLAT_STM32MP1_NS_IMAGE_OFFSET,
.image_info.image_max_size = STM32MP1_DDR_MAX_SIZE -
(PLAT_STM32MP1_NS_IMAGE_OFFSET - STM32MP1_DDR_BASE),
.image_info.image_base = PLAT_STM32MP_NS_IMAGE_OFFSET,
.image_info.image_max_size = STM32MP_DDR_MAX_SIZE -
(PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_DDR_BASE),
.next_handoff_image_id = INVALID_IMAGE_ID,
}

11
plat/st/stm32mp1/platform.mk
View File

@ -21,7 +21,8 @@ $(eval $(call add_define,STM32_TF_A_COPIES))
PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 1)))
$(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
PLAT_INCLUDES := -Iplat/st/stm32mp1/include/
PLAT_INCLUDES := -Iplat/st/common/include/
PLAT_INCLUDES += -Iplat/st/stm32mp1/include/
# Device tree
DTB_FILE_NAME ?= stm32mp157c-ev1.dtb
@ -30,7 +31,8 @@ DTC_FLAGS += -Wno-unit_address_vs_reg
include lib/libfdt/libfdt.mk
PLAT_BL_COMMON_SOURCES := plat/st/stm32mp1/stm32mp1_common.c
PLAT_BL_COMMON_SOURCES := plat/st/common/stm32mp_common.c \
plat/st/stm32mp1/stm32mp1_private.c
PLAT_BL_COMMON_SOURCES += drivers/st/uart/aarch32/stm32_console.S
@ -48,6 +50,7 @@ PLAT_BL_COMMON_SOURCES += ${LIBFDT_SRCS} \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/st/bsec/bsec.c \
drivers/st/clk/stm32mp_clkfunc.c \
drivers/st/clk/stm32mp1_clk.c \
drivers/st/clk/stm32mp1_clkfunc.c \
drivers/st/ddr/stm32mp1_ddr_helpers.c \
@ -56,8 +59,8 @@ PLAT_BL_COMMON_SOURCES += ${LIBFDT_SRCS} \
drivers/st/pmic/stm32mp_pmic.c \
drivers/st/pmic/stpmic1.c \
drivers/st/reset/stm32mp1_reset.c \
plat/st/common/stm32mp_dt.c \
plat/st/stm32mp1/stm32mp1_context.c \
plat/st/stm32mp1/stm32mp1_dt.c \
plat/st/stm32mp1/stm32mp1_helper.S \
plat/st/stm32mp1/stm32mp1_security.c
@ -65,7 +68,7 @@ BL2_SOURCES += drivers/io/io_block.c \
drivers/io/io_dummy.c \
drivers/io/io_storage.c \
drivers/st/io/io_stm32image.c \
plat/st/stm32mp1/bl2_io_storage.c \
plat/st/common/bl2_io_storage.c \
plat/st/stm32mp1/bl2_plat_setup.c
BL2_SOURCES += drivers/mmc/mmc.c \

4
plat/st/stm32mp1/sp_min/sp_min_setup.c
View File

@ -27,8 +27,6 @@
#include <plat/common/platform.h>
#include <platform_sp_min.h>
#include <stm32mp1_dt.h>
#include <stm32mp1_private.h>
/******************************************************************************
* Placeholder variables for copying the arguments that have been passed to
@ -125,7 +123,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
if ((result > 0) && (dt_uart_info.status != 0U)) {
if (console_stm32_register(dt_uart_info.base, 0,
STM32MP1_UART_BAUDRATE, &console) ==
STM32MP_UART_BAUDRATE, &console) ==
0) {
panic();
}

12
plat/st/stm32mp1/stm32mp1.ld.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,7 +17,7 @@ ENTRY(__BL2_IMAGE_START__)
MEMORY {
HEADER (rw) : ORIGIN = 0x00000000, LENGTH = 0x3000
RAM (rwx) : ORIGIN = STM32MP1_BINARY_BASE, LENGTH = STM32MP1_BINARY_SIZE
RAM (rwx) : ORIGIN = STM32MP_BINARY_BASE, LENGTH = STM32MP_BINARY_SIZE
}
SECTIONS
@ -32,7 +32,7 @@ SECTIONS
__HEADER_END__ = .;
} >HEADER
. = STM32MP1_BINARY_BASE;
. = STM32MP_BINARY_BASE;
.data . : {
. = ALIGN(PAGE_SIZE);
__DATA_START__ = .;
@ -43,7 +43,7 @@ SECTIONS
* The strongest and only alignment contraint is MMU 4K page.
* Indeed as images below will be removed, 4K pages will be re-used.
*/
. = ( STM32MP1_DTB_BASE - STM32MP1_BINARY_BASE );
. = ( STM32MP_DTB_BASE - STM32MP_BINARY_BASE );
__DTB_IMAGE_START__ = .;
*(.dtb_image*)
__DTB_IMAGE_END__ = .;
@ -53,7 +53,7 @@ SECTIONS
* The strongest and only alignment contraint is MMU 4K page.
* Indeed as images below will be removed, 4K pages will be re-used.
*/
. = ( STM32MP1_BL2_BASE - STM32MP1_BINARY_BASE );
. = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
__BL2_IMAGE_START__ = .;
*(.bl2_image*)
__BL2_IMAGE_END__ = .;
@ -63,7 +63,7 @@ SECTIONS
* The strongest and only alignment constraint is 8 words to simplify
* memraise8 assembly code.
*/
. = ( STM32MP1_BL32_BASE - STM32MP1_BINARY_BASE );
. = ( STM32MP_BL32_BASE - STM32MP_BINARY_BASE );
__BL32_IMAGE_START__ = .;
*(.bl32_image*)
__BL32_IMAGE_END__ = .;

123
plat/st/stm32mp1/stm32mp1_common.c
View File

@ -1,123 +0,0 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <platform_def.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/arm/gicv2.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <stm32mp1_private.h>
#define MAP_SRAM MAP_REGION_FLAT(STM32MP1_SRAM_BASE, \
STM32MP1_SRAM_SIZE, \
MT_MEMORY | \
MT_RW | \
MT_SECURE | \
MT_EXECUTE_NEVER)
#define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \
STM32MP1_DEVICE1_SIZE, \
MT_DEVICE | \
MT_RW | \
MT_SECURE | \
MT_EXECUTE_NEVER)
#define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \
STM32MP1_DEVICE2_SIZE, \
MT_DEVICE | \
MT_RW | \
MT_SECURE | \
MT_EXECUTE_NEVER)
#if defined(IMAGE_BL2)
static const mmap_region_t stm32mp1_mmap[] = {
MAP_SRAM,
MAP_DEVICE1,
MAP_DEVICE2,
{0}
};
#endif
#if defined(IMAGE_BL32)
static const mmap_region_t stm32mp1_mmap[] = {
MAP_SRAM,
MAP_DEVICE1,
MAP_DEVICE2,
{0}
};
#endif
void configure_mmu(void)
{
mmap_add(stm32mp1_mmap);
init_xlat_tables();
enable_mmu_svc_mon(0);
}
uintptr_t plat_get_ns_image_entrypoint(void)
{
return BL33_BASE;
}
unsigned int plat_get_syscnt_freq2(void)
{
return read_cntfrq_el0();
}
/* Functions to save and get boot context address given by ROM code */
static uintptr_t boot_ctx_address;
void stm32mp1_save_boot_ctx_address(uintptr_t address)
{
boot_ctx_address = address;
}
uintptr_t stm32mp1_get_boot_ctx_address(void)
{
return boot_ctx_address;
}
uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
{
switch (bank) {
case GPIO_BANK_A ... GPIO_BANK_K:
return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
case GPIO_BANK_Z:
return GPIOZ_BASE;
default:
panic();
}
}
/* Return clock ID on success, negative value on error */
unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
{
switch (bank) {
case GPIO_BANK_A ... GPIO_BANK_K:
return GPIOA + (bank - GPIO_BANK_A);
case GPIO_BANK_Z:
return GPIOZ;
default:
panic();
}
}
uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
{
if (bank == GPIO_BANK_Z) {
return 0;
} else {
return bank * GPIO_BANK_OFFSET;
}
}

16
plat/st/stm32mp1/stm32mp1_context.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -20,26 +20,16 @@
int stm32_save_boot_interface(uint32_t interface, uint32_t instance)
{
uint32_t tamp_clk_off = 0;
uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_ITF_BACKUP_REG_ID);
if (!stm32mp1_clk_is_enabled(RTCAPB)) {
tamp_clk_off = 1;
if (stm32mp1_clk_enable(RTCAPB) != 0) {
return -EINVAL;
}
}
stm32mp_clk_enable(RTCAPB);
mmio_clrsetbits_32(bkpr_itf_idx,
TAMP_BOOT_ITF_MASK,
((interface << 4) | (instance & 0xFU)) <<
TAMP_BOOT_ITF_SHIFT);
if (tamp_clk_off != 0U) {
if (stm32mp1_clk_disable(RTCAPB) != 0) {
return -EINVAL;
}
}
stm32mp_clk_disable(RTCAPB);
return 0;
}

90
plat/st/stm32mp1/stm32mp1_def.h
View File

@ -8,12 +8,19 @@
#define STM32MP1_DEF_H
#include <common/tbbr/tbbr_img_def.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#ifndef __ASSEMBLY__
#include <drivers/st/stm32mp1_clk.h>
#include <boot_api.h>
#include <stm32mp1_dt.h>
#include <stm32mp_common.h>
#include <stm32mp_dt.h>
#include <stm32mp_shres_helpers.h>
#include <stm32mp1_private.h>
#endif
@ -21,14 +28,13 @@
* STM32MP1 memory map related constants
******************************************************************************/
#define STM32MP1_SRAM_BASE U(0x2FFC0000)
#define STM32MP1_SRAM_SIZE U(0x00040000)
#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
#define STM32MP_SYSRAM_SIZE U(0x00040000)
/* DDR configuration */
#define STM32MP1_DDR_BASE U(0xC0000000)
#define STM32MP1_DDR_SIZE_DFLT U(0x20000000) /* 512 MB */
#define STM32MP1_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
#define STM32MP1_DDR_SPEED_DFLT 528
#define STM32MP_DDR_BASE U(0xC0000000)
#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
#define STM32MP_DDR_SPEED_DFLT 528
/* DDR power initializations */
#ifndef __ASSEMBLY__
@ -39,36 +45,36 @@ enum ddr_type {
#endif
/* Section used inside TF binaries */
#define STM32MP1_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */
#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */
/* 256 Octets reserved for header */
#define STM32MP1_HEADER_SIZE U(0x00000100)
#define STM32MP_HEADER_SIZE U(0x00000100)
#define STM32MP1_BINARY_BASE (STM32MP1_SRAM_BASE + \
STM32MP1_PARAM_LOAD_SIZE + \
STM32MP1_HEADER_SIZE)
#define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \
STM32MP_PARAM_LOAD_SIZE + \
STM32MP_HEADER_SIZE)
#define STM32MP1_BINARY_SIZE (STM32MP1_SRAM_SIZE - \
(STM32MP1_PARAM_LOAD_SIZE + \
STM32MP1_HEADER_SIZE))
#define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \
(STM32MP_PARAM_LOAD_SIZE + \
STM32MP_HEADER_SIZE))
#if STACK_PROTECTOR_ENABLED
#define STM32MP1_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */
#define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */
#else
#define STM32MP1_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */
#define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */
#endif
#define STM32MP1_BL32_BASE (STM32MP1_SRAM_BASE + \
STM32MP1_SRAM_SIZE - \
STM32MP1_BL32_SIZE)
#define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \
STM32MP_SYSRAM_SIZE - \
STM32MP_BL32_SIZE)
#if STACK_PROTECTOR_ENABLED
#define STM32MP1_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */
#define STM32MP_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */
#else
#define STM32MP1_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */
#define STM32MP_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */
#endif
#define STM32MP1_BL2_BASE (STM32MP1_BL32_BASE - \
STM32MP1_BL2_SIZE)
#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
STM32MP_BL2_SIZE)
/* BL2 and BL32/sp_min require 5 tables */
#define MAX_XLAT_TABLES 5
@ -85,12 +91,12 @@ enum ddr_type {
#endif
/* DTB initialization value */
#define STM32MP1_DTB_SIZE U(0x00004000) /* 16Ko for DTB */
#define STM32MP_DTB_SIZE U(0x00004000) /* 16Ko for DTB */
#define STM32MP1_DTB_BASE (STM32MP1_BL2_BASE - \
STM32MP1_DTB_SIZE)
#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
STM32MP_DTB_SIZE)
#define STM32MP1_BL33_BASE (STM32MP1_DDR_BASE + U(0x100000))
#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
/*******************************************************************************
* STM32MP1 device/io map related constants (used for MMU)
@ -155,12 +161,12 @@ enum ddr_type {
#define USART6_BASE U(0x44003000)
#define UART7_BASE U(0x40018000)
#define UART8_BASE U(0x40019000)
#define STM32MP1_UART_BAUDRATE U(115200)
#define STM32MP_UART_BAUDRATE U(115200)
/* For UART crash console */
#define STM32MP1_DEBUG_USART_BASE UART4_BASE
#define STM32MP_DEBUG_USART_BASE UART4_BASE
/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
#define STM32MP1_DEBUG_USART_CLK_FRQ 64000000
#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
@ -192,15 +198,15 @@ enum ddr_type {
/*******************************************************************************
* STM32MP1 SDMMC
******************************************************************************/
#define STM32MP1_SDMMC1_BASE U(0x58005000)
#define STM32MP1_SDMMC2_BASE U(0x58007000)
#define STM32MP1_SDMMC3_BASE U(0x48004000)
#define STM32MP_SDMMC1_BASE U(0x58005000)
#define STM32MP_SDMMC2_BASE U(0x58007000)
#define STM32MP_SDMMC3_BASE U(0x48004000)
#define STM32MP1_MMC_INIT_FREQ 400000 /*400 KHz*/
#define STM32MP1_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/
#define STM32MP1_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/
#define STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/
#define STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/
#define STM32MP_MMC_INIT_FREQ 400000 /*400 KHz*/
#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/
#define STM32MP_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/
#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/
#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/
/*******************************************************************************
* STM32MP1 BSEC / OTP
@ -245,4 +251,10 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
******************************************************************************/
#define I2C4_BASE U(0x5C002000)
/*******************************************************************************
* Device Tree defines
******************************************************************************/
#define DT_PWR_COMPAT "st,stm32mp1-pwr"
#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
#endif /* STM32MP1_DEF_H */

3
plat/st/stm32mp1/stm32mp1_gic.c
View File

@ -15,9 +15,6 @@
#include <lib/utils.h>
#include <plat/common/platform.h>
#include <stm32mp1_dt.h>
#include <stm32mp1_private.h>
struct stm32_gic_instance {
uint32_t cells;
uint32_t phandle_node;

13
plat/st/stm32mp1/stm32mp1_helper.S
View File

@ -10,7 +10,6 @@
#include <asm_macros.S>
#include <common/bl_common.h>
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp1_rcc.h>
#define GPIO_TX_SHIFT (DEBUG_UART_TX_GPIO_PORT << 1)
#define GPIO_TX_ALT_SHIFT ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)
@ -74,7 +73,7 @@ func plat_is_my_cpu_primary
ldcopr r0, MPIDR
ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
and r0, r1
cmp r0, #STM32MP1_PRIMARY_CPU
cmp r0, #STM32MP_PRIMARY_CPU
moveq r0, #1
movne r0, #0
bx lr
@ -143,9 +142,9 @@ func plat_crash_console_init
orr r2, r2, #DEBUG_UART_TX_EN
str r2, [r1]
ldr r0, =STM32MP1_DEBUG_USART_BASE
ldr r1, =STM32MP1_DEBUG_USART_CLK_FRQ
ldr r2, =STM32MP1_UART_BAUDRATE
ldr r0, =STM32MP_DEBUG_USART_BASE
ldr r1, =STM32MP_DEBUG_USART_CLK_FRQ
ldr r2, =STM32MP_UART_BAUDRATE
b console_stm32_core_init
endfunc plat_crash_console_init
@ -156,7 +155,7 @@ endfunc plat_crash_console_init
* ---------------------------------------------
*/
func plat_crash_console_flush
ldr r1, =STM32MP1_DEBUG_USART_BASE
ldr r1, =STM32MP_DEBUG_USART_BASE
b console_stm32_core_flush
endfunc plat_crash_console_flush
@ -172,6 +171,6 @@ endfunc plat_crash_console_flush
* ---------------------------------------------
*/
func plat_crash_console_putc
ldr r1, =STM32MP1_DEBUG_USART_BASE
ldr r1, =STM32MP_DEBUG_USART_BASE
b console_stm32_core_putc
endfunc plat_crash_console_putc

31
plat/st/stm32mp1/stm32mp1_pm.c
View File

@ -14,15 +14,11 @@
#include <drivers/arm/gic_common.h>
#include <drivers/arm/gicv2.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
#include <boot_api.h>
#include <stm32mp1_private.h>
static uintptr_t stm32_sec_entrypoint;
static uint32_t cntfrq_core0;
@ -63,7 +59,6 @@ static void stm32_cpu_standby(plat_local_state_t cpu_state)
static int stm32_pwr_domain_on(u_register_t mpidr)
{
unsigned long current_cpu_mpidr = read_mpidr_el1();
uint32_t tamp_clk_off = 0;
uint32_t bkpr_core1_addr =
tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX);
uint32_t bkpr_core1_magic =
@ -73,18 +68,13 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
return PSCI_E_INVALID_PARAMS;
}
if ((stm32_sec_entrypoint < STM32MP1_SRAM_BASE) ||
(stm32_sec_entrypoint > (STM32MP1_SRAM_BASE +
(STM32MP1_SRAM_SIZE - 1)))) {
if ((stm32_sec_entrypoint < STM32MP_SYSRAM_BASE) ||
(stm32_sec_entrypoint > (STM32MP_SYSRAM_BASE +
(STM32MP_SYSRAM_SIZE - 1)))) {
return PSCI_E_INVALID_ADDRESS;
}
if (!stm32mp1_clk_is_enabled(RTCAPB)) {
tamp_clk_off = 1;
if (stm32mp1_clk_enable(RTCAPB) != 0) {
panic();
}
}
stm32mp_clk_enable(RTCAPB);
cntfrq_core0 = read_cntfrq_el0();
@ -94,14 +84,10 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
/* Write magic number in backup register */
mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER);
if (tamp_clk_off != 0U) {
if (stm32mp1_clk_disable(RTCAPB) != 0) {
panic();
}
}
stm32mp_clk_disable(RTCAPB);
/* Generate an IT to core 1 */
gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP1_SECONDARY_CPU);
gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP_SECONDARY_CPU);
return PSCI_E_SUCCESS;
}
@ -163,7 +149,8 @@ static void __dead2 stm32_system_off(void)
static void __dead2 stm32_system_reset(void)
{
mmio_setbits_32(RCC_BASE + RCC_MP_GRSTCSETR, RCC_MP_GRSTCSETR_MPSYSRST);
mmio_setbits_32(stm32mp_rcc_base() + RCC_MP_GRSTCSETR,
RCC_MP_GRSTCSETR_MPSYSRST);
/* Loop in case system reset is not immediately caught */
for ( ; ; ) {
@ -197,7 +184,7 @@ static int stm32_validate_power_state(unsigned int power_state,
static int stm32_validate_ns_entrypoint(uintptr_t entrypoint)
{
/* The non-secure entry point must be in DDR */
if (entrypoint < STM32MP1_DDR_BASE) {
if (entrypoint < STM32MP_DDR_BASE) {
return PSCI_E_INVALID_ADDRESS;
}

55
plat/st/stm32mp1/stm32mp1_private.c Normal file
View File

@ -0,0 +1,55 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#define MAP_SRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
STM32MP_SYSRAM_SIZE, \
MT_MEMORY | \
MT_RW | \
MT_SECURE | \
MT_EXECUTE_NEVER)
#define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \
STM32MP1_DEVICE1_SIZE, \
MT_DEVICE | \
MT_RW | \
MT_SECURE | \
MT_EXECUTE_NEVER)
#define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \
STM32MP1_DEVICE2_SIZE, \
MT_DEVICE | \
MT_RW | \
MT_SECURE | \
MT_EXECUTE_NEVER)
#if defined(IMAGE_BL2)
static const mmap_region_t stm32mp1_mmap[] = {
MAP_SRAM,
MAP_DEVICE1,
MAP_DEVICE2,
{0}
};
#endif
#if defined(IMAGE_BL32)
static const mmap_region_t stm32mp1_mmap[] = {
MAP_SRAM,
MAP_DEVICE1,
MAP_DEVICE2,
{0}
};
#endif
void configure_mmu(void)
{
mmap_add(stm32mp1_mmap);
init_xlat_tables();
enable_mmu_svc_mon(0);
}

22
plat/st/stm32mp1/stm32mp1_security.c
View File

@ -11,13 +11,9 @@
#include <common/debug.h>
#include <drivers/arm/tzc400.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <lib/mmio.h>
#include <stm32mp1_dt.h>
#include <stm32mp1_private.h>
/*******************************************************************************
* Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
* and allow Non-Secure masters full access.
@ -25,7 +21,7 @@
static void init_tzc400(void)
{
unsigned long long region_base, region_top;
unsigned long long ddr_base = STM32MP1_DDR_BASE;
unsigned long long ddr_base = STM32MP_DDR_BASE;
unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size();
tzc400_init(STM32MP1_TZC_BASE);
@ -65,14 +61,8 @@ static void init_tzc400(void)
******************************************************************************/
static void early_init_tzc400(void)
{
if (stm32mp1_clk_enable(TZC1) != 0) {
ERROR("Cannot enable TZC1 clock\n");
panic();
}
if (stm32mp1_clk_enable(TZC2) != 0) {
ERROR("Cannot enable TZC2 clock\n");
panic();
}
stm32mp_clk_enable(TZC1);
stm32mp_clk_enable(TZC2);
tzc400_init(STM32MP1_TZC_BASE);
@ -83,9 +73,9 @@ static void early_init_tzc400(void)
* same configuration to all filters in the TZC.
*/
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
STM32MP1_DDR_BASE,
STM32MP1_DDR_BASE +
(STM32MP1_DDR_MAX_SIZE - 1U),
STM32MP_DDR_BASE,
STM32MP_DDR_BASE +
(STM32MP_DDR_MAX_SIZE - 1U),
TZC_REGION_S_RDWR,
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID));