Merge pull request #1027 from vchong/960_bl32_optee_support
hikey960 updates
This commit is contained in:
davidcunado-arm
GitHub
commit
37debcc6f9
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@ -14,6 +14,9 @@ Code Locations
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- ARM Trusted Firmware:
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`link <https://github.com/ARM-software/arm-trusted-firmware>`__
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- OP-TEE:
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`link <https://github.com/OP-TEE/optee_os>`__
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- edk2:
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`link <https://github.com/96boards-hikey/edk2/tree/testing/hikey960_v2.5>`__
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@ -24,7 +27,7 @@ Code Locations
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`link <https://github.com/96boards-hikey/l-loader/tree/testing/hikey960_v1.2>`__
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- uefi-tools:
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`link <https://github.com/96boards-hikey/uefi-tools/tree/hikey960_v1>`__
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`link <https://git.linaro.org/uefi/uefi-tools.git>`__
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Build Procedure
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---------------
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@ -56,26 +59,26 @@ Build Procedure
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.. code:: shell
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BUILD_OPTION=DEBUG
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export AARCH64_TOOLCHAIN=GCC48
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export AARCH64_TOOLCHAIN=GCC5
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export UEFI_TOOLS_DIR=${BUILD_PATH}/uefi-tools
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export EDK2_DIR=${BUILD_PATH}/edk2
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EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey960/${BUILD_OPTION}_${AARCH64_TOOLCHAIN}
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cd ${EDK2_DIR}
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# Build UEFI & ARM Trust Firmware
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${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware hikey960
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${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey960
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# Generate l-loader.bin
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cd ${BUILD_PATH}/l-loader
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ln -sf ${EDK2_OUTPUT_DIR}/FV/bl1.bin
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ln -sf ${EDK2_OUTPUT_DIR}/FV/fip.bin
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ln -sf ${EDK2_OUTPUT_DIR}/FV/BL33_AP_UEFI.fd
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python gen_loader.py -o l-loader.bin --img_bl1=bl1.bin --img_ns_bl1u=BL33_AP_UEFI.fd
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python gen_loader_hikey960.py -o l-loader.bin --img_bl1=bl1.bin --img_ns_bl1u=BL33_AP_UEFI.fd
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- Generate partition table.
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*Make sure that you're using the sgdisk in the l-loader directory.*
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.. code:: shell
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$PTABLE=aosp-32g SECTOR_SIZE=4096 SGDISK=./sgdisk bash -x generate_ptable.sh
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PTABLE=aosp-32g SECTOR_SIZE=4096 SGDISK=./sgdisk bash -x generate_ptable.sh
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Setup Console
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-------------
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@ -99,6 +102,13 @@ Setup Console
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2004:telnet:0:/dev/ttyUSB0:115200 8DATABITS NONE 1STOPBIT banner
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- Start ser2net
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.. code:: shell
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$sudo killall ser2net
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$sudo ser2net -u
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- Open the console.
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.. code:: shell
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@ -126,7 +136,7 @@ Boot UEFI in recovery mode
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$vi config
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# The content of config file
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./sec_user_xloader.img 0x00020000
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./sec_usb_xloader.img 0x00020000
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./sec_uce_boot.img 0x6A908000
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./l-loader.bin 0x1AC00000
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@ -37,6 +37,10 @@
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HIKEY960_UFS_DESC_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
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TSP_SEC_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*
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* Table of regions for different BL stages to map using the MMU.
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* This doesn't include Trusted RAM as the 'mem_layout' argument passed to
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@ -56,6 +60,7 @@ static const mmap_region_t hikey960_mmap[] = {
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static const mmap_region_t hikey960_mmap[] = {
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MAP_DDR,
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MAP_DEVICE,
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MAP_TSP_MEM,
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{0}
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};
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#endif
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@ -63,6 +68,15 @@ static const mmap_region_t hikey960_mmap[] = {
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#if IMAGE_BL31
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static const mmap_region_t hikey960_mmap[] = {
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MAP_DEVICE,
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MAP_TSP_MEM,
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{0}
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};
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#endif
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#if IMAGE_BL32
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static const mmap_region_t hikey960_mmap[] = {
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MAP_DEVICE,
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MAP_DDR,
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{0}
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};
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#endif
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@ -177,6 +177,41 @@ void bl2_plat_set_bl31_ep_info(image_info_t *image,
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DISABLE_ALL_EXCEPTIONS);
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}
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/*******************************************************************************
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* Before calling this function BL32 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL32 and set SPSR and security state.
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* On Hikey we only set the security state of the entrypoint
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******************************************************************************/
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#ifdef BL32_BASE
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void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
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entry_point_info_t *bl32_ep_info)
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{
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SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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bl32_ep_info->spsr = 0;
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}
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/*******************************************************************************
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* Populate the extents of memory available for loading BL32
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******************************************************************************/
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void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
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{
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/*
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* Populate the extents of memory available for loading BL32.
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*/
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bl32_meminfo->total_base = BL32_BASE;
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bl32_meminfo->free_base = BL32_BASE;
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bl32_meminfo->total_size =
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(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
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bl32_meminfo->free_size =
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(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
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}
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#endif /* BL32_BASE */
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void bl2_plat_set_bl33_ep_info(image_info_t *image,
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entry_point_info_t *bl33_ep_info)
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{
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@ -16,6 +16,25 @@
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#define DEVICE_BASE 0xE0000000
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#define DEVICE_SIZE 0x20000000
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/* Memory location options for TSP */
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#define HIKEY960_SRAM_ID 0
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#define HIKEY960_DRAM_ID 1
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/*
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* DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
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* regions:
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* - Secure DDR (default is the top 16MB) used by OP-TEE
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* - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
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* - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
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* - Non-secure DDR (8MB) reserved for OP-TEE's future use
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*/
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#define DDR_SEC_SIZE 0x01000000
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#define DDR_SEC_BASE 0x3F000000
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#define DDR_SDP_SIZE 0x00400000
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#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
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DDR_SDP_SIZE)
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/*
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* PL011 related constants
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*/
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@ -69,6 +69,10 @@ static const io_uuid_spec_t bl31_uuid_spec = {
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.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
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};
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static const io_uuid_spec_t bl32_uuid_spec = {
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.uuid = UUID_SECURE_PAYLOAD_BL32,
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};
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static const io_uuid_spec_t bl33_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
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};
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@ -94,6 +98,11 @@ static const struct plat_io_policy policies[] = {
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(uintptr_t)&bl31_uuid_spec,
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check_fip
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},
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[BL32_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl32_uuid_spec,
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check_fip
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},
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[BL33_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl33_uuid_spec,
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@ -63,6 +63,27 @@
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#define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */
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#define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */
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/*
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* BL3-2 specific defines.
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*/
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/*
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* The TSP currently executes from TZC secured area of DRAM.
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*/
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#define BL32_DRAM_BASE DDR_SEC_BASE
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#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
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#if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
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#define BL32_BASE BL32_DRAM_BASE
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#define BL32_LIMIT BL32_DRAM_LIMIT
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#elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID)
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#error "SRAM storage of TSP payload is currently unsupported"
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#else
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#error "Currently unsupported HIKEY960_TSP_LOCATION_ID value"
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#endif
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#define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */
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#define NS_BL1U_SIZE (0x00100000)
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#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
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@ -70,7 +91,7 @@
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#define HIKEY960_NS_IMAGE_OFFSET (0x1AC18000) /* offset in l-loader */
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#define HIKEY960_NS_TMP_OFFSET (0x1AE00000)
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#define SCP_BL2_BASE BL31_BASE
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#define SCP_BL2_BASE BL31_BASE /* 1AC5_8000 */
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#define SCP_MEM_BASE (0x89C80000)
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#define SCP_MEM_SIZE (0x00040000)
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@ -80,7 +101,7 @@
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*/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31
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#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31 || IMAGE_BL32
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#define MAX_XLAT_TABLES 3
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#endif
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@ -4,13 +4,23 @@
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# On Hikey960, the TSP can execute from TZC secure area in DRAM.
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HIKEY960_TSP_RAM_LOCATION := dram
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ifeq (${HIKEY960_TSP_RAM_LOCATION}, dram)
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HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_DRAM_ID
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else ifeq (${HIKEY960_TSP_RAM_LOCATION}, sram)
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HIKEY960_TSP_RAM_LOCATION_ID := HIKEY960_SRAM_ID
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else
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$(error "Currently unsupported HIKEY960_TSP_RAM_LOCATION value")
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endif
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CRASH_CONSOLE_BASE := PL011_UART6_BASE
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COLD_BOOT_SINGLE_CPU := 1
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PROGRAMMABLE_RESET_ADDRESS := 1
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# Process flags
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$(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID))
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$(eval $(call add_define,CRASH_CONSOLE_BASE))
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$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
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ENABLE_PLAT_COMPAT := 0
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@ -63,3 +73,8 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
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plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c \
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plat/hisilicon/hikey960/drivers/ipc/hisi_ipc.c \
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${HIKEY960_GIC_SOURCES}
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# Enable workarounds for selected Cortex-A53 errata.
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ERRATA_A53_836870 := 1
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ERRATA_A53_843419 := 1
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ERRATA_A53_855873 := 1
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