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Tegra210: secure PMC hardware block 

This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and System Resume.

The sc7entry-fw, running on the COP, needs access to the PMC block
to enter System Suspend state, so "unlock" the PMC block before
passing control to the COP.

Change-Id: I00e39a49ae6b9f8c8eafe0cf7ff63fe6a67fdccf
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
This commit is contained in:
kalyani chidambaram 2018-04-09 15:18:02 -07:00 committed by Varun Wadekar
parent dd4f0885a0
commit 37f760241e
2 changed files with 19 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
View File

@ -394,6 +394,15 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
*/
tegra_reset_all_dma_masters();
/*
* Mark PMC as accessible to the non-secure world
* to allow the COP to execute System Suspend
* sequence
*/
val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
val &= ~PMC_SECURITY_EN_BIT;
mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
/* clean up IRAM of any cruft */
zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE,
TEGRA_IRAM_A_SIZE);
@ -480,12 +489,14 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
tegra_bpmp_resume();
}
/* sc7entry-fw is part of TZDRAM area */
if (plat_params->sc7entry_fw_base != 0U) {
/* sc7entry-fw is part of TZDRAM area */
offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
plat_params->tzdram_size + offset);
}
if (!tegra_chipid_is_t210_b01()) {
/* restrict PMC access to secure world */
val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
val |= PMC_SECURITY_EN_BIT;

7
plat/nvidia/tegra/soc/t210/plat_setup.c
View File

@ -236,6 +236,13 @@ void plat_late_platform_setup(void)
val |= PMC_SECURITY_EN_BIT;
mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
}
if (!tegra_chipid_is_t210_b01()) {
/* restrict PMC access to secure world */
val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
val |= PMC_SECURITY_EN_BIT;
mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
}
}
/*******************************************************************************