Merge changes Id7d4f5df,If82542cc,I0ba80057,I75a443db,Ifa18b4fc, ... into integration
* changes: feat(nxp/common/ocram): add driver for OCRAM initialization feat(plat/nxp/common): add EESR register definition fix(plat/nxp/ls1028a): fix compile error when enable fuse provision fix(drivers/nxp/sfp): fix compile warning fix(plat/nxp/ls1028a): define endianness of scfg and gpio fix(nxp/scfg): fix endianness checking
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commit
381d685021
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@ -326,7 +326,7 @@ static int prog_ospr1(struct fuse_hdr_t *fuse_hdr,
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struct sfp_ccsr_regs_t *sfp_ccsr_regs)
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{
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int ret;
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uint32_t mask;
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uint32_t mask = 0;
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#ifdef NXP_SFP_VER_3_4
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if (((fuse_hdr->flags >> FLAG_MC_SHIFT) & 0x1) != 0) {
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@ -44,7 +44,7 @@
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#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
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#define scfg_clrsetbits32(a, clear, set) \
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mmio_clrsetbits_32((uintptr_t)(a), clear, set)
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#elif defined(NXP_GUR_LE)
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#elif defined(NXP_SCFG_LE)
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#define scfg_in32(a) mmio_read_32((uintptr_t)(a))
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#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v)
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#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
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@ -56,6 +56,11 @@
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#define RCPM_POWMGTCSR_OFFSET 0x130
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#define RCPM_IPPDEXPCR0_OFFSET 0x140
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#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
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#endif
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#endif /* NXP_RCPM_ADDR */
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#define DCFG_SBEESR2_ADDR 0x20140534
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#define DCFG_MBEESR2_ADDR 0x20140544
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/* SBEESR and MBEESR bit mask */
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#define OCRAM_EESR_MASK 0x00000060
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#endif /* SOC_DEFAULT_HELPER_MACROS_H */
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@ -79,4 +79,9 @@
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#define ENABLE_WUO 0x10
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#endif /* NXP_CCN_ADDR */
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#define DCFG_SBEESR2_ADDR 0x00100534
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#define DCFG_MBEESR2_ADDR 0x00100544
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/* SBEESR and MBEESR bit mask */
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#define OCRAM_EESR_MASK 0x00000008
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#endif /* SOC_DEFAULT_HELPER_MACROS_H */
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@ -0,0 +1,71 @@
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <soc_default_base_addr.h>
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#include <soc_default_helper_macros.h>
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.global ocram_init
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/*
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* void ocram_init(uintptr_t start_addr, size_t size)
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*
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* This function will do OCRAM ECC.
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* OCRAM is initialized with 64-bit writes and then a write
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* performed to address 0x0010_0534 with the value 0x0000_0008.
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*
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* x0: start_addr
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* x1: size in bytes
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* Called from C
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*/
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func ocram_init
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/* save the aarch32/64 non-volatile registers */
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stp x4, x5, [sp, #-16]!
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stp x6, x7, [sp, #-16]!
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stp x8, x9, [sp, #-16]!
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stp x10, x11, [sp, #-16]!
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stp x12, x13, [sp, #-16]!
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stp x18, x30, [sp, #-16]!
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/* convert bytes to 64-byte chunks */
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lsr x1, x1, #6
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1:
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/* for each location, read and write-back */
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dc ivac, x0
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dsb sy
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ldp x4, x5, [x0]
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ldp x6, x7, [x0, #16]
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ldp x8, x9, [x0, #32]
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ldp x10, x11, [x0, #48]
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stp x4, x5, [x0]
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stp x6, x7, [x0, #16]
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stp x8, x9, [x0, #32]
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stp x10, x11, [x0, #48]
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dc cvac, x0
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sub x1, x1, #1
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cbz x1, 2f
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add x0, x0, #64
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b 1b
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2:
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/* Clear OCRAM ECC status bit in SBEESR2 and MBEESR2 */
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ldr w1, =OCRAM_EESR_MASK
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ldr x0, =DCFG_SBEESR2_ADDR
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str w1, [x0]
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ldr x0, =DCFG_MBEESR2_ADDR
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str w1, [x0]
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/* restore the aarch32/64 non-volatile registers */
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ldp x18, x30, [sp], #16
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ldp x12, x13, [sp], #16
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ldp x10, x11, [sp], #16
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ldp x8, x9, [sp], #16
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ldp x6, x7, [sp], #16
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ldp x4, x5, [sp], #16
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ret
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endfunc ocram_init
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@ -0,0 +1,13 @@
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef OCRAM_H
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#define OCRAM_H
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void ocram_init(uintptr_t start_addr, size_t size);
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#endif /* OCRAM_H */
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@ -0,0 +1,14 @@
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#
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# Copyright 2021 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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#
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PLAT_OCRAM_PATH := $(PLAT_COMMON_PATH)/ocram
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OCRAM_SOURCES := ${PLAT_OCRAM_PATH}/$(ARCH)/ocram.S
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BL2_SOURCES += ${OCRAM_SOURCES}
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PLAT_INCLUDES += -I${PLAT_COMMON_PATH}/ocram
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@ -112,3 +112,8 @@ endif
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ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
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$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
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endif
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ifeq (${OCRAM_ECC_EN},yes)
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$(eval $(call add_define,CONFIG_OCRAM_ECC_EN))
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include ${PLAT_COMMON_PATH}/ocram/ocram.mk
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endif
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@ -16,6 +16,9 @@
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <ls_interconnect.h>
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#include <mmio.h>
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#ifdef POLICY_FUSE_PROVISION
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#include <nxp_gpio.h>
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#endif
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#if TRUSTED_BOARD_BOOT
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#include <nxp_smmu.h>
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#endif
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@ -81,6 +84,15 @@ unsigned int plat_get_syscnt_freq2(void)
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}
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#ifdef IMAGE_BL2
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#ifdef POLICY_FUSE_PROVISION
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static gpio_init_info_t gpio_init_data = {
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.gpio1_base_addr = NXP_GPIO1_ADDR,
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.gpio2_base_addr = NXP_GPIO2_ADDR,
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.gpio3_base_addr = NXP_GPIO3_ADDR,
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};
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#endif
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void soc_preload_setup(void)
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{
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}
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@ -88,6 +88,8 @@ NXP_SNVS_ENDIANNESS := LE
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NXP_ESDHC_ENDIANNESS := LE
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NXP_QSPI_ENDIANNESS := LE
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NXP_FSPI_ENDIANNESS := LE
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NXP_SCFG_ENDIANNESS := LE
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NXP_GPIO_ENDIANNESS := LE
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NXP_SFP_VER := 3_4
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