andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge changes from topic "tegra-downstream-07092020" into integration 

* changes:
  Tegra: platform: add function to check t194 chip
  Tegra: common: make plat_psci_ops routines static
This commit is contained in:
Manish Pandey 2020-08-19 09:37:38 +00:00 committed by TrustedFirmware Code Review
parent 3ee8e4d8de 43d22073d4
commit 38294532db
4 changed files with 21 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
plat/nvidia/tegra/common/tegra_platform.c
View File

@ -108,6 +108,13 @@ bool tegra_chipid_is_t210_b01(void)
return (tegra_chipid_is_t210() && (tegra_get_chipid_major() == 0x2U));
}
bool tegra_chipid_is_t194(void)
{
uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
return (chip_id == TEGRA_CHIPID_TEGRA19);
}
/*
* Read the chip ID value and derive the platform
*/

24
plat/nvidia/tegra/common/tegra_pm.c
View File

@ -34,7 +34,7 @@ extern uint64_t tegra_sec_entry_point;
* the appropriate State-ID field within the `power_state` parameter which can
* be utilized in `pwr_domain_suspend()` to suspend to system affinity level.
******************************************************************************/
void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
static void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
{
/* all affinities use system suspend state id */
for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) {
@ -45,7 +45,7 @@ void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
/*******************************************************************************
* Handler called when an affinity instance is about to enter standby.
******************************************************************************/
void tegra_cpu_standby(plat_local_state_t cpu_state)
static void tegra_cpu_standby(plat_local_state_t cpu_state)
{
u_register_t saved_scr_el3;
@ -84,7 +84,7 @@ void tegra_cpu_standby(plat_local_state_t cpu_state)
* Handler called when an affinity instance is about to be turned on. The
* level and mpidr determine the affinity instance.
******************************************************************************/
int32_t tegra_pwr_domain_on(u_register_t mpidr)
static int32_t tegra_pwr_domain_on(u_register_t mpidr)
{
return tegra_soc_pwr_domain_on(mpidr);
}
@ -93,7 +93,7 @@ int32_t tegra_pwr_domain_on(u_register_t mpidr)
* Handler called when a power domain is about to be turned off. The
* target_state encodes the power state that each level should transition to.
******************************************************************************/
void tegra_pwr_domain_off(const psci_power_state_t *target_state)
static void tegra_pwr_domain_off(const psci_power_state_t *target_state)
{
(void)tegra_soc_pwr_domain_off(target_state);
}
@ -113,7 +113,7 @@ void tegra_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_sta
* Handler called when a power domain is about to be suspended. The
* target_state encodes the power state that each level should transition to.
******************************************************************************/
void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
static void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
{
(void)tegra_soc_pwr_domain_suspend(target_state);
@ -132,7 +132,7 @@ void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
* Handler called at the end of the power domain suspend sequence. The
* target_state encodes the power state that each level should transition to.
******************************************************************************/
__dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
static __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
*target_state)
{
/* call the chip's power down handler */
@ -147,7 +147,7 @@ __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
* being turned off earlier. The target_state encodes the low power state that
* each level has woken up from.
******************************************************************************/
void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
static void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
const plat_params_from_bl2_t *plat_params;
@ -198,7 +198,7 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
* having been suspended earlier. The target_state encodes the low power state
* that each level has woken up from.
******************************************************************************/
void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
static void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
{
tegra_pwr_domain_on_finish(target_state);
}
@ -206,7 +206,7 @@ void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
/*******************************************************************************
* Handler called when the system wants to be powered off
******************************************************************************/
__dead2 void tegra_system_off(void)
static __dead2 void tegra_system_off(void)
{
INFO("Powering down system...\n");
@ -216,7 +216,7 @@ __dead2 void tegra_system_off(void)
/*******************************************************************************
* Handler called when the system wants to be restarted.
******************************************************************************/
__dead2 void tegra_system_reset(void)
static __dead2 void tegra_system_reset(void)
{
INFO("Restarting system...\n");
@ -232,7 +232,7 @@ __dead2 void tegra_system_reset(void)
/*******************************************************************************
* Handler called to check the validity of the power state parameter.
******************************************************************************/
int32_t tegra_validate_power_state(uint32_t power_state,
static int32_t tegra_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state)
{
assert(req_state != NULL);
@ -243,7 +243,7 @@ int32_t tegra_validate_power_state(uint32_t power_state,
/*******************************************************************************
* Platform handler called to check the validity of the non secure entrypoint.
******************************************************************************/
int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint)
static int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint)
{
int32_t ret = PSCI_E_INVALID_ADDRESS;

2
plat/nvidia/tegra/include/tegra_platform.h
View File

@ -30,6 +30,7 @@
#define TEGRA_CHIPID_TEGRA13 U(0x13)
#define TEGRA_CHIPID_TEGRA21 U(0x21)
#define TEGRA_CHIPID_TEGRA18 U(0x18)
#define TEGRA_CHIPID_TEGRA19 U(0x19)
/*******************************************************************************
* JEDEC Standard Manufacturer's Identification Code and Bank ID
@ -52,6 +53,7 @@ bool tegra_chipid_is_t132(void);
bool tegra_chipid_is_t186(void);
bool tegra_chipid_is_t210(void);
bool tegra_chipid_is_t210_b01(void);
bool tegra_chipid_is_t194(void);
/*
* Tegra platform identifiers

13
plat/nvidia/tegra/include/tegra_private.h
View File

@ -112,19 +112,6 @@ __dead2 void tegra_soc_prepare_system_off(void);
plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
const plat_local_state_t *states,
uint32_t ncpu);
void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state);
void tegra_cpu_standby(plat_local_state_t cpu_state);
int32_t tegra_pwr_domain_on(u_register_t mpidr);
void tegra_pwr_domain_off(const psci_power_state_t *target_state);
void tegra_pwr_domain_suspend(const psci_power_state_t *target_state);
void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state);
void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state);
void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state);
__dead2 void tegra_system_off(void);
__dead2 void tegra_system_reset(void);
int32_t tegra_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state);
int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint);
/* Declarations for tegraXXX_pm.c */
int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl);