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Do not enable SVE on pre-v8.2 platforms 

Pre-v8.2 platforms such as the Juno platform does not have
the Scalable Vector Extensions implemented and so the build
option ENABLE_SVE is set to zero.

This has a minor performance improvement with no functional
impact.

Change-Id: Ib072735db7a0247406f8b60e325b7e28b1e04ad1
Signed-off-by: David Cunado <david.cunado@arm.com>
This commit is contained in:
David Cunado 2017-10-31 23:19:21 +00:00
parent 1a853370ff
commit 3872fc2d1f
14 changed files with 35 additions and 3 deletions
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3
plat/arm/board/juno/platform.mk
View File

@ -86,6 +86,9 @@ ENABLE_PLAT_COMPAT := 0
# Enable memory map related constants optimisation
ARM_BOARD_OPTIMISE_MEM := 1
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
include plat/arm/board/common/board_css.mk
include plat/arm/common/arm_common.mk
include plat/arm/soc/common/soc_css.mk

3
plat/compat/plat_compat.mk
View File

@ -18,3 +18,6 @@ PLAT_BL_COMMON_SOURCES += plat/compat/aarch64/plat_helpers_compat.S
BL31_SOURCES += plat/common/plat_psci_common.c \
plat/compat/plat_pm_compat.c \
plat/compat/plat_topology_compat.c
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0

1
plat/hisilicon/hikey/platform.mk
View File

@ -24,6 +24,7 @@ PLAT_PARTITION_MAX_ENTRIES := 12
PLAT_PL061_MAX_GPIOS := 160
COLD_BOOT_SINGLE_CPU := 1
PROGRAMMABLE_RESET_ADDRESS := 1
ENABLE_SVE_FOR_NS := 0
# Process flags
$(eval $(call add_define,HIKEY_TSP_RAM_LOCATION_ID))

1
plat/hisilicon/hikey960/platform.mk
View File

@ -20,6 +20,7 @@ endif
CRASH_CONSOLE_BASE := PL011_UART6_BASE
COLD_BOOT_SINGLE_CPU := 1
PROGRAMMABLE_RESET_ADDRESS := 1
ENABLE_SVE_FOR_NS := 0
# Process flags
$(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID))

2
plat/hisilicon/poplar/platform.mk
View File

@ -13,6 +13,7 @@ ENABLE_PLAT_COMPAT := 0
ERRATA_A53_855873 := 1
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ENABLE_SVE_FOR_NS := 0
ARM_GIC_ARCH := 2
$(eval $(call add_define,ARM_GIC_ARCH))
@ -69,4 +70,3 @@ BL31_SOURCES += \
plat/hisilicon/poplar/bl31_plat_setup.c \
plat/hisilicon/poplar/plat_topology.c \
plat/hisilicon/poplar/plat_pm.c

2
plat/mediatek/mt6795/platform.mk
View File

@ -66,3 +66,5 @@ PROGRAMMABLE_RESET_ADDRESS := 1
$(eval $(call add_define,MTK_SIP_KERNEL_BOOT_ENABLE))
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0

3
plat/mediatek/mt8173/platform.mk
View File

@ -70,3 +70,6 @@ ERRATA_A53_855873 := 1
PROGRAMMABLE_RESET_ADDRESS := 1
$(eval $(call add_define,MTK_SIP_SET_AUTHORIZED_SECURE_REG_ENABLE))
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0

3
plat/nvidia/tegra/platform.mk
View File

@ -29,6 +29,9 @@ SEPARATE_CODE_AND_RODATA := 1
# do not use coherent memory
USE_COHERENT_MEM := 0
# do not enable SVE
ENABLE_SVE_FOR_NS := 0
include plat/nvidia/tegra/common/tegra_common.mk
include ${SOC_DIR}/platform_${TARGET_SOC}.mk

3
plat/qemu/platform.mk
View File

@ -153,3 +153,6 @@ endif
# Process flags
$(eval $(call add_define,BL32_RAM_LOCATION_ID))
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0

5
plat/rockchip/rk3328/platform.mk
View File

@ -48,7 +48,10 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/soc/soc.c
ENABLE_PLAT_COMPAT := 0
ENABLE_PLAT_COMPAT := 0
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
$(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER))
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0

5
plat/rockchip/rk3368/platform.mk
View File

@ -48,6 +48,9 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/drivers/ddr/ddr_rk3368.c \
ENABLE_PLAT_COMPAT := 0
ENABLE_PLAT_COMPAT := 0
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0

3
plat/rockchip/rk3399/platform.mk
View File

@ -92,3 +92,6 @@ $(eval $(call MAKE_PREREQ_DIR,${BUILD_M0},${BUILD_PLAT}))
.PHONY: $(RK3399M0FW)
$(RK3399M0FW): | ${BUILD_M0}
$(MAKE) -C ${RK_PLAT_SOC}/drivers/m0 BUILD=$(abspath ${BUILD_PLAT}/m0)
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0

1
plat/socionext/uniphier/platform.mk
View File

@ -10,6 +10,7 @@ override ERROR_DEPRECATED := 1
override LOAD_IMAGE_V2 := 1
override USE_COHERENT_MEM := 1
override USE_TBBR_DEFS := 1
override ENABLE_SVE_FOR_NS := 0
# Cortex-A53 revision r0p4-51rel0
# needed for LD20, unneeded for LD11, PXs3 (no ACE)

3
plat/xilinx/zynqmp/platform.mk
View File

@ -11,6 +11,9 @@ A53_DISABLE_NON_TEMPORAL_HINT := 0
SEPARATE_CODE_AND_RODATA := 1
override RESET_TO_BL31 := 1
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
ifdef ZYNQMP_ATF_MEM_BASE
$(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))