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marvell: comphy: cp110: add support for SATA comphy polarity invert 

The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doesn't require
SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards.

Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
This commit is contained in:
Grzegorz Jaszczyk 2020-01-21 17:02:10 +01:00 committed by Marcin Wojtas
parent 8fa1340892
commit 38f6daca7a
6 changed files with 48 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/marvell/comphy/comphy-cp110.h
View File

@ -355,6 +355,14 @@
#define HPIPE_CDR_LOCK_DET_EN_MASK \
(0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET)
#define HPIPE_SYNC_PATTERN_REG 0x090
#define HPIPE_SYNC_PATTERN_TXD_INV_OFFSET 10
#define HPIPE_SYNC_PATTERN_TXD_INV_MASK \
(0x1 << HPIPE_SYNC_PATTERN_TXD_INV_OFFSET)
#define HPIPE_SYNC_PATTERN_RXD_INV_OFFSET 11
#define HPIPE_SYNC_PATTERN_RXD_INV_MASK \
(0x1 << HPIPE_SYNC_PATTERN_RXD_INV_OFFSET)
#define HPIPE_INTERFACE_REG 0x94
#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
#define HPIPE_INTERFACE_GEN_MAX_MASK \

29
drivers/marvell/comphy/phy-comphy-cp110.c
View File

@ -323,12 +323,33 @@ int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base, uint8_t comphy_index)
return ret;
}
static void mvebu_cp110_polarity_invert(uintptr_t addr, uint8_t phy_polarity_invert)
{
uint32_t mask, data;
/* Set RX / TX polarity */
data = mask = 0x0U;
if ((phy_polarity_invert & COMPHY_POLARITY_TXD_INVERT) != 0) {
data |= (1 << HPIPE_SYNC_PATTERN_TXD_INV_OFFSET);
mask |= HPIPE_SYNC_PATTERN_TXD_INV_MASK;
debug("%s: inverting TX polarity\n", __func__);
}
if ((phy_polarity_invert & COMPHY_POLARITY_RXD_INVERT) != 0) {
data |= (1 << HPIPE_SYNC_PATTERN_RXD_INV_OFFSET);
mask |= HPIPE_SYNC_PATTERN_RXD_INV_MASK;
debug("%s: inverting RX polarity\n", __func__);
}
reg_set(addr, data, mask);
}
static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
uint8_t comphy_index, uint32_t comphy_mode)
{
uintptr_t hpipe_addr, sd_ip_addr, comphy_addr;
uint32_t mask, data;
uint8_t ap_nr, cp_nr;
uint8_t ap_nr, cp_nr, phy_polarity_invert;
int ret = 0;
debug_enter();
@ -338,6 +359,7 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
const struct sata_params *sata_static_values =
&sata_static_values_tab[ap_nr][cp_nr][comphy_index];
phy_polarity_invert = sata_static_values->polarity_invert;
/* configure phy selector for SATA */
mvebu_cp110_comphy_set_phy_selector(comphy_base,
@ -629,6 +651,11 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
HPIPE_PWR_CTR_RST_DFE_MASK);
if (phy_polarity_invert != 0)
mvebu_cp110_polarity_invert(hpipe_addr + HPIPE_SYNC_PATTERN_REG,
phy_polarity_invert);
/* SW reset for interrupt logic */
reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET,

6
drivers/marvell/comphy/phy-comphy-cp110.h
View File

@ -76,6 +76,8 @@ struct sata_params {
uint8_t g2_rx_selmupi;
uint8_t g3_rx_selmupi;
uint8_t polarity_invert;
_Bool valid;
};
@ -89,3 +91,7 @@ int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
uint8_t comphy_index);
int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index,
uint32_t comphy_mode, uint32_t command);
#define COMPHY_POLARITY_NO_INVERT 0
#define COMPHY_POLARITY_TXD_INVERT 1
#define COMPHY_POLARITY_RXD_INVERT 2

1
drivers/marvell/comphy/phy-default-porting-layer.h
View File

@ -45,6 +45,7 @@ static const struct sata_params
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
},
};

4
plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h
View File

@ -92,6 +92,7 @@ static const struct sata_params
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy1 */
{ 0 }, /* Comphy2 */
@ -116,6 +117,7 @@ static const struct sata_params
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy3 */
{ 0 }, /* Comphy4 */
@ -146,6 +148,7 @@ static const struct sata_params
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy1 */
{ 0 }, /* Comphy2 */
@ -170,6 +173,7 @@ static const struct sata_params
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
}, /* Comphy3 */
{ 0 }, /* Comphy4 */

1
plat/marvell/octeontx/otx2/t91/t9130/board/phy-porting-layer.h
View File

@ -131,6 +131,7 @@ SATA_PARAMS sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
.g3_rx_selmupf = 0x2,
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
.g3_rx_selmupi = 0x2,
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
.valid = 0x1
},
};