From cc47e1ada6d9a4234d8ca6547008ddc10e6e6568 Mon Sep 17 00:00:00 2001 From: Dimitris Papastamos Date: Wed, 14 Jun 2017 14:47:36 +0100 Subject: [PATCH 1/2] juno/aarch32: Restore `SCP_BOOT_CFG_ADDR` to the cold boot value Before BL2 loads the SCP ram firmware, `SCP_BOOT_CFG_ADDR` specifies the primary core. After the SCP ram firmware has started executing, `SCP_BOOT_CFG_ADDR` is modified. This is not normally an issue but the Juno AArch32 boot flow is a special case. BL1 does a warm reset into AArch32 and the core jumps to the `sp_min` entrypoint. This is effectively a `RESET_TO_SP_MIN` configuration. `sp_min` has to be able to determine the primary core and hence we need to restore `SCP_BOOT_CFG_ADDR` to the cold boot value before `sp_min` runs. This magically worked when booting on A53 because the core index was zero and it just so happened to match with the new value in `SCP_BOOT_CFG_ADDR`. Change-Id: I105425c680cf6238948625c1d1017b01d3517c01 Signed-off-by: Dimitris Papastamos --- plat/arm/board/juno/juno_bl2_setup.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/plat/arm/board/juno/juno_bl2_setup.c b/plat/arm/board/juno/juno_bl2_setup.c index 8f18531a1..abceb0f5e 100644 --- a/plat/arm/board/juno/juno_bl2_setup.c +++ b/plat/arm/board/juno/juno_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,4 +29,28 @@ int bl2_plat_handle_post_image_load(unsigned int image_id) return err; } + +/* + * We need to override some of the platform functions when booting SP_MIN + * on Juno AArch32. + */ + +static unsigned int scp_boot_config; + +void bl2_early_platform_setup(meminfo_t *mem_layout) +{ + arm_bl2_early_platform_setup(mem_layout); + + /* Save SCP Boot config before it gets overwritten by SCP_BL2 loading */ + VERBOSE("BL2: Saving SCP Boot config = 0x%x\n", scp_boot_config); + scp_boot_config = mmio_read_32(SCP_BOOT_CFG_ADDR); +} + +void bl2_platform_setup(void) +{ + arm_bl2_platform_setup(); + + mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config); + VERBOSE("BL2: Restored SCP Boot config = 0x%x\n", scp_boot_config); +} #endif /* JUNO_AARCH32_EL3_RUNTIME */ From 35bd2dda0f28ba628745fa952682703e26d5e833 Mon Sep 17 00:00:00 2001 From: Dimitris Papastamos Date: Mon, 19 Jun 2017 14:15:31 +0100 Subject: [PATCH 2/2] juno: Invalidate all caches before warm reset to AArch32 state. On Juno AArch32, the L2 cache may contain garbage after the warm reset from AArch64 to AArch32. This is all fine until the MMU is configured and the data caches enabled. To avoid fetching stale data from the L2 unified cache, invalidate it before the warm reset to AArch32 state. Change-Id: I7d27e810692c02c3e83c9f31de67f6bae59a960a Signed-off-by: Dimitris Papastamos --- plat/arm/board/juno/aarch64/juno_helpers.S | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/plat/arm/board/juno/aarch64/juno_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S index 8d00a1a73..5e7f08e77 100644 --- a/plat/arm/board/juno/aarch64/juno_helpers.S +++ b/plat/arm/board/juno/aarch64/juno_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -266,6 +266,16 @@ endfunc plat_get_my_entrypoint * to AArch32 mode is then requested by writing into RMR_EL3. */ func juno_reset_to_aarch32_state + /* + * Invalidate all caches before the warm reset to AArch32 state. + * This is required on the Juno AArch32 boot flow because the L2 + * unified cache may contain code and data from when the processor + * was still executing in AArch64 state. This code only runs on + * the primary core, all other cores are powered down. + */ + mov x0, #DCISW + bl dcsw_op_all + emit_movw w0, BL32_BASE emit_movt w1, BL32_BASE /* opcode "bx r0" to branch using r0 in AArch32 mode */