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build(intel): enable access to on-chip ram in BL31 for N5X 

This adds the ncore ccu access and enable access to the
on-chip ram for N5X device in BL31.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I713f6e93d33b6e91705547477ca32cfba5c8c13d
This commit is contained in:
Boon Khai Ng 2021-05-21 22:56:37 +08:00 committed by Sieu Mun Tang
parent f571183b06
commit 39f262cfb4
4 changed files with 19 additions and 3 deletions
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13
plat/intel/soc/common/drivers/ccu/ncore_ccu.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -107,6 +107,17 @@ void bypass_ocram_firewall(void)
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
}
void ncore_enable_ocram_firewall(void)
{
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF2),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF3),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4),
OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
}
uint32_t init_ncore_ccu(void)
{
uint32_t status;

3
plat/intel/soc/common/drivers/ccu/ncore_ccu.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -104,5 +104,6 @@ typedef struct coh_ss_id {
} coh_ss_id_t;
uint32_t init_ncore_ccu(void);
void ncore_enable_ocram_firewall(void);
#endif

3
plat/intel/soc/n5x/bl31_plat_setup.c
View File

@ -13,6 +13,7 @@
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables.h>
#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
@ -115,6 +116,8 @@ void bl31_platform_setup(void)
(uint64_t)plat_secondary_cpus_bl31_entry);
mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
ncore_enable_ocram_firewall();
}
const mmap_region_t plat_dm_mmap[] = {

3
plat/intel/soc/n5x/platform.mk
View File

@ -25,7 +25,8 @@ PLAT_BL_COMMON_SOURCES := \
lib/xlat_tables/xlat_tables_common.c \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S \
plat/intel/soc/common/socfpga_delay_timer.c
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/drivers/ccu/ncore_ccu.c
BL2_SOURCES +=