Add "Project Denver" CPU support
Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is fully ARMv8 architecture compatible. Each of the two Denver cores implements a 7-way superscalar microarchitecture (up to 7 concurrent micro-ops can be executed per clock), and includes a 128KB 4-way L1 instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2 cache, which services both cores. Denver implements an innovative process called Dynamic Code Optimization, which optimizes frequently used software routines at runtime into dense, highly tuned microcode-equivalent routines. These are stored in a dedicated, 128MB main-memory-based optimization cache. After being read into the instruction cache, the optimized micro-ops are executed, re-fetched and executed from the instruction cache as long as needed and capacity allows. Effectively, this reduces the need to re-optimize the software routines. Instead of using hardware to extract the instruction-level parallelism (ILP) inherent in the code, Denver extracts the ILP once via software techniques, and then executes those routines repeatedly, thus amortizing the cost of ILP extraction over the many execution instances. Denver also features new low latency power-state transitions, in addition to extensive power-gating and dynamic voltage and clock scaling based on workloads. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DENVER_H__
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#define __DENVER_H__
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/* MIDR for Denver v1.0 */
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#define DENVER_1_0_MIDR 0x4E0F0000
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/* CPU state ids - implementation defined */
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#define DENVER_CPU_STATE_POWER_DOWN 0x3
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#endif /* __DENVER_H__ */
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <denver.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* ---------------------------------------------
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* Disable debug interfaces
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* ---------------------------------------------
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*/
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func denver_disable_ext_debug
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mov x0, #1
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msr osdlr_el1, x0
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isb
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dsb sy
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ret
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endfunc denver_disable_ext_debug
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/* ----------------------------------------------------
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* Enable dynamic code optimizer (DCO)
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* ----------------------------------------------------
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*/
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func denver_enable_dco
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mrs x0, mpidr_el1
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and x0, x0, #0xF
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mov x1, #1
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lsl x1, x1, x0
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msr s3_0_c15_c0_2, x1
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isb
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ret
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endfunc denver_enable_dco
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/* ----------------------------------------------------
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* Disable dynamic code optimizer (DCO)
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* ----------------------------------------------------
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*/
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func denver_disable_dco
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/* turn off background work */
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mrs x0, mpidr_el1
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and x0, x0, #0xF
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mov x1, #1
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lsl x1, x1, x0
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lsl x2, x1, #16
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msr s3_0_c15_c0_2, x2
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isb
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/* wait till the background work turns off */
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1: mrs x2, s3_0_c15_c0_2
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lsr x2, x2, #32
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and w2, w2, 0xFFFF
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and x2, x2, x1
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cbnz x2, 1b
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ret
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endfunc denver_disable_dco
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/* -------------------------------------------------
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* The CPU Ops reset function for Denver.
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* -------------------------------------------------
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*/
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func denver_reset_func
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mov x19, x30
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/* ----------------------------------------------------
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* Enable dynamic code optimizer (DCO)
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* ----------------------------------------------------
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*/
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bl denver_enable_dco
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ret x19
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endfunc denver_reset_func
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Denver.
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* ----------------------------------------------------
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*/
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func denver_core_pwr_dwn
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mov x19, x30
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/* ----------------------------------------------------
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* We enter the 'core power gated with ARM state not
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* retained' power state during CPU power down. We let
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* DCO know that we expect to enter this power state
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* by writing to the ACTLR_EL1 register.
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* ----------------------------------------------------
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*/
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mov x0, #DENVER_CPU_STATE_POWER_DOWN
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msr actlr_el1, x0
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/* ---------------------------------------------
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* Force DCO to be quiescent
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* ---------------------------------------------
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*/
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bl denver_disable_dco
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/* ---------------------------------------------
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* Force the debug interfaces to be quiescent
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* ---------------------------------------------
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*/
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bl denver_disable_ext_debug
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ret x19
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endfunc denver_core_pwr_dwn
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/* -------------------------------------------------------
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* The CPU Ops cluster power down function for Denver.
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* -------------------------------------------------------
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*/
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func denver_cluster_pwr_dwn
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ret
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endfunc denver_cluster_pwr_dwn
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/* ---------------------------------------------
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* This function provides Denver specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.denver_regs, "aS"
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denver_regs: /* The ascii list of register names to be reported */
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.asciz "actlr_el1", ""
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func denver_cpu_reg_dump
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adr x6, denver_regs
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mrs x8, ACTLR_EL1
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ret
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endfunc denver_cpu_reg_dump
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declare_cpu_ops denver, DENVER_1_0_MIDR
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