feat(plat/nxp/ls1043a): add ls1043a soc support
The LS1043A processor was NXP's first quad-core, 64-bit Arm based processor for embedded networking. The old implementation in tf-a (plat/layerscape/board/ls1043/) is removed, and this patch is adding it back, it is using the unified software component and architecture with all the other Layerscape platforms. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: rocket <rod.dorris@nxp.com> Change-Id: Ia3877530fae6479bd4a33bbe46b0c0d28ab43160
This commit is contained in:
Jiafei Pan
parent
ff4ec0a036
commit
3b0de91825
File diff suppressed because it is too large
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/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl plat_reset_handler
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.globl platform_mem_init
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func platform_mem1_init
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ret
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endfunc platform_mem1_init
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func platform_mem_init
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ret
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endfunc platform_mem_init
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func apply_platform_errata
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ret
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endfunc apply_platform_errata
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func plat_reset_handler
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mov x29, x30
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bl apply_platform_errata
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#if defined(IMAGE_BL31)
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ldr x0, =POLICY_SMMU_PAGESZ_64K
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cbz x0, 1f
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/* Set the SMMU page size in the sACR register */
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bl _set_smmu_pagesz_64
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#endif
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1:
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mov x30, x29
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ret
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endfunc plat_reset_handler
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/*
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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*/
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func plat_secondary_cold_boot_setup
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/* ls1043a does not do cold boot for secondary CPU */
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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/*
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, 0x0
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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@ -0,0 +1,175 @@
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/*
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* Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018, 2020-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NS_ACCESS_H
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#define NS_ACCESS_H
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#include <csu.h>
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enum csu_cslx_ind {
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CSU_CSLX_PCIE2_IO = 0,
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CSU_CSLX_PCIE1_IO,
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CSU_CSLX_MG2TPR_IP,
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CSU_CSLX_IFC_MEM,
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CSU_CSLX_OCRAM,
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CSU_CSLX_GIC,
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CSU_CSLX_PCIE1,
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CSU_CSLX_OCRAM2,
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CSU_CSLX_QSPI_MEM,
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CSU_CSLX_PCIE2,
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CSU_CSLX_SATA,
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CSU_CSLX_USB1,
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CSU_CSLX_QM_BM_SWPORTAL,
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CSU_CSLX_PCIE3 = 16,
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CSU_CSLX_PCIE3_IO,
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CSU_CSLX_USB3 = 20,
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CSU_CSLX_USB2,
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CSU_CSLX_PFE = 23,
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CSU_CSLX_SERDES = 32,
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CSU_CSLX_QDMA,
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CSU_CSLX_LPUART2,
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CSU_CSLX_LPUART1,
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CSU_CSLX_LPUART4,
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CSU_CSLX_LPUART3,
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CSU_CSLX_LPUART6,
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CSU_CSLX_LPUART5,
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CSU_CSLX_DSPI1 = 41,
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CSU_CSLX_QSPI,
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CSU_CSLX_ESDHC,
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CSU_CSLX_IFC = 45,
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CSU_CSLX_I2C1,
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CSU_CSLX_USB_2,
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CSU_CSLX_I2C3 = 48,
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CSU_CSLX_I2C2,
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CSU_CSLX_DUART2 = 50,
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CSU_CSLX_DUART1,
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CSU_CSLX_WDT2,
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CSU_CSLX_WDT1,
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CSU_CSLX_EDMA,
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CSU_CSLX_SYS_CNT,
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CSU_CSLX_DMA_MUX2,
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CSU_CSLX_DMA_MUX1,
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CSU_CSLX_DDR,
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CSU_CSLX_QUICC,
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CSU_CSLX_DCFG_CCU_RCPM = 60,
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CSU_CSLX_SECURE_BOOTROM,
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CSU_CSLX_SFP,
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CSU_CSLX_TMU,
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CSU_CSLX_SECURE_MONITOR,
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CSU_CSLX_SCFG,
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CSU_CSLX_FM = 66,
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CSU_CSLX_SEC5_5,
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CSU_CSLX_BM,
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CSU_CSLX_QM,
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CSU_CSLX_GPIO2 = 70,
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CSU_CSLX_GPIO1,
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CSU_CSLX_GPIO4,
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CSU_CSLX_GPIO3,
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CSU_CSLX_PLATFORM_CONT,
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CSU_CSLX_CSU,
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CSU_CSLX_IIC4 = 77,
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CSU_CSLX_WDT4,
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CSU_CSLX_WDT3,
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CSU_CSLX_ESDHC2 = 80,
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CSU_CSLX_WDT5 = 81,
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CSU_CSLX_SAI2,
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CSU_CSLX_SAI1,
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CSU_CSLX_SAI4,
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CSU_CSLX_SAI3,
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CSU_CSLX_FTM2 = 86,
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CSU_CSLX_FTM1,
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CSU_CSLX_FTM4,
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CSU_CSLX_FTM3,
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CSU_CSLX_FTM6 = 90,
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CSU_CSLX_FTM5,
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CSU_CSLX_FTM8,
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CSU_CSLX_FTM7,
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CSU_CSLX_DSCR = 121,
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};
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struct csu_ns_dev_st ns_dev[] = {
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{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
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{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
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{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
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{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
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{CSU_CSLX_OCRAM, CSU_S_SUP_RW},
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{CSU_CSLX_GIC, CSU_ALL_RW},
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{CSU_CSLX_PCIE1, CSU_ALL_RW},
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{CSU_CSLX_OCRAM2, CSU_S_SUP_RW},
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{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
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{CSU_CSLX_PCIE2, CSU_ALL_RW},
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{CSU_CSLX_SATA, CSU_ALL_RW},
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{CSU_CSLX_USB1, CSU_ALL_RW},
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{CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
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{CSU_CSLX_PCIE3, CSU_ALL_RW},
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{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
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{CSU_CSLX_USB3, CSU_ALL_RW},
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{CSU_CSLX_USB2, CSU_ALL_RW},
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{CSU_CSLX_PFE, CSU_ALL_RW},
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{CSU_CSLX_SERDES, CSU_ALL_RW},
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{CSU_CSLX_QDMA, CSU_ALL_RW},
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{CSU_CSLX_LPUART2, CSU_ALL_RW},
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{CSU_CSLX_LPUART1, CSU_ALL_RW},
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{CSU_CSLX_LPUART4, CSU_ALL_RW},
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{CSU_CSLX_LPUART3, CSU_ALL_RW},
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{CSU_CSLX_LPUART6, CSU_ALL_RW},
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{CSU_CSLX_LPUART5, CSU_ALL_RW},
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{CSU_CSLX_DSPI1, CSU_ALL_RW},
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{CSU_CSLX_QSPI, CSU_ALL_RW},
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{CSU_CSLX_ESDHC, CSU_ALL_RW},
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{CSU_CSLX_IFC, CSU_ALL_RW},
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{CSU_CSLX_I2C1, CSU_ALL_RW},
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{CSU_CSLX_USB_2, CSU_ALL_RW},
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{CSU_CSLX_I2C3, CSU_ALL_RW},
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{CSU_CSLX_I2C2, CSU_ALL_RW},
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{CSU_CSLX_DUART2, CSU_ALL_RW},
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{CSU_CSLX_DUART1, CSU_ALL_RW},
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{CSU_CSLX_WDT2, CSU_ALL_RW},
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{CSU_CSLX_WDT1, CSU_ALL_RW},
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{CSU_CSLX_EDMA, CSU_ALL_RW},
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{CSU_CSLX_SYS_CNT, CSU_ALL_RW},
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{CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
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{CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
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{CSU_CSLX_DDR, CSU_ALL_RW},
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{CSU_CSLX_QUICC, CSU_ALL_RW},
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{CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
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{CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
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{CSU_CSLX_SFP, CSU_ALL_RW},
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{CSU_CSLX_TMU, CSU_ALL_RW},
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{CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
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{CSU_CSLX_SCFG, CSU_ALL_RW},
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{CSU_CSLX_FM, CSU_ALL_RW},
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{CSU_CSLX_SEC5_5, CSU_ALL_RW},
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{CSU_CSLX_BM, CSU_ALL_RW},
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{CSU_CSLX_QM, CSU_ALL_RW},
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{CSU_CSLX_GPIO2, CSU_ALL_RW},
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{CSU_CSLX_GPIO1, CSU_ALL_RW},
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{CSU_CSLX_GPIO4, CSU_ALL_RW},
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{CSU_CSLX_GPIO3, CSU_ALL_RW},
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{CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
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{CSU_CSLX_CSU, CSU_ALL_RW},
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{CSU_CSLX_IIC4, CSU_ALL_RW},
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{CSU_CSLX_WDT4, CSU_ALL_RW},
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{CSU_CSLX_WDT3, CSU_ALL_RW},
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{CSU_CSLX_ESDHC2, CSU_ALL_RW},
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{CSU_CSLX_WDT5, CSU_ALL_RW},
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{CSU_CSLX_SAI2, CSU_ALL_RW},
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{CSU_CSLX_SAI1, CSU_ALL_RW},
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{CSU_CSLX_SAI4, CSU_ALL_RW},
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{CSU_CSLX_SAI3, CSU_ALL_RW},
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{CSU_CSLX_FTM2, CSU_ALL_RW},
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{CSU_CSLX_FTM1, CSU_ALL_RW},
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{CSU_CSLX_FTM4, CSU_ALL_RW},
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{CSU_CSLX_FTM3, CSU_ALL_RW},
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{CSU_CSLX_FTM6, CSU_ALL_RW},
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{CSU_CSLX_FTM5, CSU_ALL_RW},
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{CSU_CSLX_FTM8, CSU_ALL_RW},
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{CSU_CSLX_FTM7, CSU_ALL_RW},
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{CSU_CSLX_DSCR, CSU_ALL_RW},
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};
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#endif /* NS_ACCESS_H */
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/*
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* Copyright 2017-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_H
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#define SOC_H
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/* Chassis specific defines - common across SoC's of a particular platform */
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#include "dcfg_lsch2.h"
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#include "soc_default_base_addr.h"
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#include "soc_default_helper_macros.h"
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/* DDR Regions Info */
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#define NUM_DRAM_REGIONS 3
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#define NXP_DRAM0_ADDR 0x80000000
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#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */
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#define NXP_DRAM1_ADDR 0x880000000
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#define NXP_DRAM1_MAX_SIZE 0x780000000 /* 30 GB */
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#define NXP_DRAM2_ADDR 0x8800000000
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#define NXP_DRAM2_MAX_SIZE 0x7800000000 /* 480 GB */
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/* DRAM0 Size defined in platform_def.h */
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#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
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/*
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* P23: 23 x 23 package
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* A: without security
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* AE: with security
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* SVR Definition (not include major and minor rev)
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*/
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#define SVR_LS1023A 0x879209
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#define SVR_LS1023AE 0x879208
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#define SVR_LS1023A_P23 0x87920B
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#define SVR_LS1023AE_P23 0x87920A
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#define SVR_LS1043A 0x879201
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#define SVR_LS1043AE 0x879200
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#define SVR_LS1043A_P23 0x879203
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#define SVR_LS1043AE_P23 0x879202
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/* Number of cores in platform */
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#define PLATFORM_CORE_COUNT 4
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#define NUMBER_OF_CLUSTERS 1
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#define CORES_PER_CLUSTER 4
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/* set to 0 if the clusters are not symmetrical */
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#define SYMMETRICAL_CLUSTERS 1
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/*
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* Required LS standard platform porting definitions
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* for CCI-400
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*/
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#define NXP_CCI_CLUSTER0_SL_IFACE_IX 4
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/* ls1043 version info for GIC configuration */
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#define REV1_0 0x10
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#define REV1_1 0x11
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#define GIC_ADDR_BIT 31
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/* Errata */
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#define NXP_ERRATUM_A009663
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#define NXP_ERRATUM_A009942
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#define NUM_OF_DDRC 1
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/* Defines required for using XLAT tables from ARM common code */
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40)
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/* Clock Divisors */
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#define NXP_PLATFORM_CLK_DIVIDER 1
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#define NXP_UART_CLK_DIVIDER 1
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/*
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* Set this switch to 1 if you need to keep the debug block
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* clocked during system power-down.
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*/
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#define DEBUG_ACTIVE 0
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#define IPPDEXPCR_MAC1_1 0x80000000 // DEVDISR2_FMAN1_MAC1
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#define IPPDEXPCR_MAC1_2 0x40000000 // DEVDISR2_FMAN1_MAC2
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#define IPPDEXPCR_MAC1_3 0x20000000 // DEVDISR2_FMAN1_MAC3
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#define IPPDEXPCR_MAC1_4 0x10000000 // DEVDISR2_FMAN1_MAC4
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#define IPPDEXPCR_MAC1_5 0x08000000 // DEVDISR2_FMAN1_MAC5
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#define IPPDEXPCR_MAC1_6 0x04000000 // DEVDISR2_FMAN1_MAC6
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#define IPPDEXPCR_MAC1_9 0x00800000 // DEVDISR2_FMAN1_MAC9
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#define IPPDEXPCR_I2C1 0x00080000 // DEVDISR5_I2C_1
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#define IPPDEXPCR_LPUART1 0x00040000 // DEVDISR5_LPUART1
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#define IPPDEXPCR_FLX_TMR1 0x00020000 // DEVDISR5_FLX_TMR
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#define IPPDEXPCR_OCRAM1 0x00010000 // DEVDISR5_OCRAM1
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#define IPPDEXPCR_GPIO1 0x00000040 // DEVDISR5_GPIO
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#define IPPDEXPCR_FM1 0x00000008 // DEVDISR2_FMAN1
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#define IPPDEXPCR_MASK1 0xFC800008 // overrides for DEVDISR2
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#define IPPDEXPCR_MASK2 0x000F0040 // overriddes for DEVDISR5
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#define IPSTPCR0_VALUE 0xA000C201
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#define IPSTPCR1_VALUE 0x00000080
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#define IPSTPCR2_VALUE 0x000C0000
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#define IPSTPCR3_VALUE 0x38000000
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#if (DEBUG_ACTIVE)
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#define IPSTPCR4_VALUE 0x10833BFC
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#else
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#define IPSTPCR4_VALUE 0x10A33BFC
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#endif
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#define DEVDISR1_QE 0x00000001
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#define DEVDISR1_SEC 0x00000200
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#define DEVDISR1_USB1 0x00004000
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#define DEVDISR1_SATA 0x00008000
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#define DEVDISR1_USB2 0x00010000
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#define DEVDISR1_USB3 0x00020000
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#define DEVDISR1_DMA2 0x00400000
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#define DEVDISR1_DMA1 0x00800000
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#define DEVDISR1_ESDHC 0x20000000
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#define DEVDISR1_PBL 0x80000000
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#define DEVDISR2_FMAN1 0x00000080
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#define DEVDISR2_FMAN1_MAC9 0x00800000
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#define DEVDISR2_FMAN1_MAC6 0x04000000
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#define DEVDISR2_FMAN1_MAC5 0x08000000
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#define DEVDISR2_FMAN1_MAC4 0x10000000
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#define DEVDISR2_FMAN1_MAC3 0x20000000
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#define DEVDISR2_FMAN1_MAC2 0x40000000
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#define DEVDISR2_FMAN1_MAC1 0x80000000
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#define DEVDISR3_BMAN 0x00040000
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#define DEVDISR3_QMAN 0x00080000
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#define DEVDISR3_PEX3 0x20000000
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#define DEVDISR3_PEX2 0x40000000
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#define DEVDISR3_PEX1 0x80000000
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|
||||
#define DEVDISR4_QSPI 0x08000000
|
||||
#define DEVDISR4_DUART2 0x10000000
|
||||
#define DEVDISR4_DUART1 0x20000000
|
||||
|
||||
#define DEVDISR5_ICMMU 0x00000001
|
||||
#define DEVDISR5_I2C_1 0x00000002
|
||||
#define DEVDISR5_I2C_2 0x00000004
|
||||
#define DEVDISR5_I2C_3 0x00000008
|
||||
#define DEVDISR5_I2C_4 0x00000010
|
||||
#define DEVDISR5_WDG_5 0x00000020
|
||||
#define DEVDISR5_WDG_4 0x00000040
|
||||
#define DEVDISR5_WDG_3 0x00000080
|
||||
#define DEVDISR5_DSPI1 0x00000100
|
||||
#define DEVDISR5_WDG_2 0x00000200
|
||||
#define DEVDISR5_FLX_TMR 0x00000400
|
||||
#define DEVDISR5_WDG_1 0x00000800
|
||||
#define DEVDISR5_LPUART6 0x00001000
|
||||
#define DEVDISR5_LPUART5 0x00002000
|
||||
#define DEVDISR5_LPUART3 0x00008000
|
||||
#define DEVDISR5_LPUART2 0x00010000
|
||||
#define DEVDISR5_LPUART1 0x00020000
|
||||
#define DEVDISR5_DBG 0x00200000
|
||||
#define DEVDISR5_GPIO 0x00400000
|
||||
#define DEVDISR5_IFC 0x00800000
|
||||
#define DEVDISR5_OCRAM2 0x01000000
|
||||
#define DEVDISR5_OCRAM1 0x02000000
|
||||
#define DEVDISR5_LPUART4 0x10000000
|
||||
#define DEVDISR5_DDR 0x80000000
|
||||
#define DEVDISR5_MEM 0x80000000
|
||||
|
||||
#define DEVDISR1_VALUE 0xA0C3C201
|
||||
#define DEVDISR2_VALUE 0xCC0C0080
|
||||
#define DEVDISR3_VALUE 0xE00C0000
|
||||
#define DEVDISR4_VALUE 0x38000000
|
||||
#if (DEBUG_ACTIVE)
|
||||
#define DEVDISR5_VALUE 0x10833BFC
|
||||
#else
|
||||
#define DEVDISR5_VALUE 0x10A33BFC
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PWR mgmt features supported in the soc-specific code:
|
||||
* value == 0x0 the soc code does not support this feature
|
||||
* value != 0x0 the soc code supports this feature
|
||||
*/
|
||||
#define SOC_CORE_RELEASE 0x1
|
||||
#define SOC_CORE_RESTART 0x1
|
||||
#define SOC_CORE_OFF 0x1
|
||||
#define SOC_CORE_STANDBY 0x1
|
||||
#define SOC_CORE_PWR_DWN 0x1
|
||||
#define SOC_CLUSTER_STANDBY 0x1
|
||||
#define SOC_CLUSTER_PWR_DWN 0x1
|
||||
#define SOC_SYSTEM_STANDBY 0x1
|
||||
#define SOC_SYSTEM_PWR_DWN 0x1
|
||||
#define SOC_SYSTEM_OFF 0x1
|
||||
#define SOC_SYSTEM_RESET 0x1
|
||||
|
||||
/* PSCI-specific defines */
|
||||
#define SYSTEM_PWR_DOMAINS 1
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
|
||||
NUMBER_OF_CLUSTERS + \
|
||||
SYSTEM_PWR_DOMAINS)
|
||||
|
||||
/* Power state coordination occurs at the system level */
|
||||
#define PLAT_PD_COORD_LVL MPIDR_AFFLVL2
|
||||
#define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL
|
||||
|
||||
/* Local power state for power domains in Run state */
|
||||
#define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN
|
||||
|
||||
/* define retention state */
|
||||
#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
|
||||
#define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE
|
||||
|
||||
/* define power-down state */
|
||||
#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
|
||||
#define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
|
||||
|
||||
/*
|
||||
* Some data must be aligned on the biggest cache line size in the platform.
|
||||
* This is known only to the platform as it might have a combination of
|
||||
* integrated and external caches.
|
||||
* CACHE_WRITEBACK_GRANULE is defined in soc.def
|
||||
*/
|
||||
|
||||
/* One cache line needed for bakery locks on ARM platforms */
|
||||
#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
/* CCI slave interfaces */
|
||||
static const int cci_map[] = {
|
||||
NXP_CCI_CLUSTER0_SL_IFACE_IX,
|
||||
};
|
||||
void soc_init_lowlevel(void);
|
||||
void soc_init_percpu(void);
|
||||
void _soc_set_start_addr(unsigned long addr);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* SOC_H */
|
||||
|
|
@ -0,0 +1,435 @@
|
|||
/*
|
||||
* Copyright 2018-2021 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include <arch.h>
|
||||
#include <caam.h>
|
||||
#include <cassert.h>
|
||||
#include <cci.h>
|
||||
#include <common/debug.h>
|
||||
#include <dcfg.h>
|
||||
#ifdef I2C_INIT
|
||||
#include <i2c.h>
|
||||
#endif
|
||||
#include <lib/mmio.h>
|
||||
#include <lib/xlat_tables/xlat_tables_v2.h>
|
||||
#include <ls_interconnect.h>
|
||||
#ifdef POLICY_FUSE_PROVISION
|
||||
#include <nxp_gpio.h>
|
||||
#endif
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
#include <nxp_smmu.h>
|
||||
#endif
|
||||
#include <nxp_timer.h>
|
||||
#include <plat_console.h>
|
||||
#include <plat_gic.h>
|
||||
#include <plat_tzc380.h>
|
||||
#include <scfg.h>
|
||||
#if defined(NXP_SFP_ENABLED)
|
||||
#include <sfp.h>
|
||||
#endif
|
||||
|
||||
#include <errata.h>
|
||||
#include <ns_access.h>
|
||||
#ifdef CONFIG_OCRAM_ECC_EN
|
||||
#include <ocram.h>
|
||||
#endif
|
||||
#include <plat_common.h>
|
||||
#include <platform_def.h>
|
||||
#include <soc.h>
|
||||
|
||||
static dcfg_init_info_t dcfg_init_data = {
|
||||
.g_nxp_dcfg_addr = NXP_DCFG_ADDR,
|
||||
.nxp_sysclk_freq = NXP_SYSCLK_FREQ,
|
||||
.nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
|
||||
.nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
|
||||
};
|
||||
|
||||
|
||||
/* Function to return the SoC SYS CLK */
|
||||
unsigned int get_sys_clk(void)
|
||||
{
|
||||
return NXP_SYSCLK_FREQ;
|
||||
}
|
||||
|
||||
/*
|
||||
* Function returns the base counter frequency
|
||||
* after reading the first entry at CNTFID0 (0x20 offset).
|
||||
*
|
||||
* Function is used by:
|
||||
* 1. ARM common code for PSCI management.
|
||||
* 2. ARM Generic Timer init.
|
||||
*
|
||||
*/
|
||||
unsigned int plat_get_syscnt_freq2(void)
|
||||
{
|
||||
unsigned int counter_base_frequency;
|
||||
|
||||
counter_base_frequency = get_sys_clk()/4;
|
||||
|
||||
return counter_base_frequency;
|
||||
}
|
||||
|
||||
#ifdef IMAGE_BL2
|
||||
|
||||
static struct soc_type soc_list[] = {
|
||||
SOC_ENTRY(LS1023A, LS1023A, 1, 2),
|
||||
SOC_ENTRY(LS1023AE, LS1023AE, 1, 2),
|
||||
SOC_ENTRY(LS1023A_P23, LS1023A_P23, 1, 2),
|
||||
SOC_ENTRY(LS1023AE_P23, LS1023AE_P23, 1, 2),
|
||||
SOC_ENTRY(LS1043A, LS1043A, 1, 4),
|
||||
SOC_ENTRY(LS1043AE, LS1043AE, 1, 4),
|
||||
SOC_ENTRY(LS1043A_P23, LS1043A_P23, 1, 4),
|
||||
SOC_ENTRY(LS1043AE_P23, LS1043AE_P23, 1, 4),
|
||||
};
|
||||
|
||||
#ifdef POLICY_FUSE_PROVISION
|
||||
static gpio_init_info_t gpio_init_data = {
|
||||
.gpio1_base_addr = NXP_GPIO1_ADDR,
|
||||
.gpio2_base_addr = NXP_GPIO2_ADDR,
|
||||
.gpio3_base_addr = NXP_GPIO3_ADDR,
|
||||
.gpio4_base_addr = NXP_GPIO4_ADDR,
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Function to set the base counter frequency at
|
||||
* the first entry of the Frequency Mode Table,
|
||||
* at CNTFID0 (0x20 offset).
|
||||
*
|
||||
* Set the value of the pirmary core register cntfrq_el0.
|
||||
*/
|
||||
static void set_base_freq_CNTFID0(void)
|
||||
{
|
||||
/*
|
||||
* Below register specifies the base frequency of the system counter.
|
||||
* As per NXP Board Manuals:
|
||||
* The system counter always works with SYS_REF_CLK/4 frequency clock.
|
||||
*
|
||||
*/
|
||||
unsigned int counter_base_frequency = get_sys_clk()/4;
|
||||
|
||||
/*
|
||||
* Setting the frequency in the Frequency modes table.
|
||||
*
|
||||
* Note: The value for ls1046ardb board at this offset
|
||||
* is not RW as stated. This offset have the
|
||||
* fixed value of 100000400 Hz.
|
||||
*
|
||||
* The below code line has no effect.
|
||||
* Keeping it for other platforms where it has effect.
|
||||
*/
|
||||
mmio_write_32(NXP_TIMER_ADDR + CNTFID_OFF, counter_base_frequency);
|
||||
|
||||
write_cntfrq_el0(counter_base_frequency);
|
||||
}
|
||||
|
||||
void soc_preload_setup(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function implements soc specific erratas
|
||||
* This is called before DDR is initialized or MMU is enabled
|
||||
******************************************************************************/
|
||||
void soc_early_init(void)
|
||||
{
|
||||
uint8_t num_clusters, cores_per_cluster;
|
||||
dram_regions_info_t *dram_regions_info = get_dram_regions_info();
|
||||
|
||||
#ifdef CONFIG_OCRAM_ECC_EN
|
||||
ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
|
||||
#endif
|
||||
dcfg_init(&dcfg_init_data);
|
||||
#ifdef POLICY_FUSE_PROVISION
|
||||
gpio_init(&gpio_init_data);
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
#endif
|
||||
#if LOG_LEVEL > 0
|
||||
/* Initialize the console to provide early debug support */
|
||||
|
||||
plat_console_init(NXP_CONSOLE_ADDR,
|
||||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
|
||||
#endif
|
||||
set_base_freq_CNTFID0();
|
||||
|
||||
/* Enable snooping on SEC read and write transactions */
|
||||
scfg_setbits32((void *)(NXP_SCFG_ADDR + SCFG_SNPCNFGCR_OFFSET),
|
||||
SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP);
|
||||
|
||||
/*
|
||||
* Initialize Interconnect for this cluster during cold boot.
|
||||
* No need for locks as no other CPU is active.
|
||||
*/
|
||||
cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
|
||||
|
||||
/*
|
||||
* Enable Interconnect coherency for the primary CPU's cluster.
|
||||
*/
|
||||
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
|
||||
plat_ls_interconnect_enter_coherency(num_clusters);
|
||||
|
||||
#if TRUSTED_BOARD_BOOT
|
||||
uint32_t mode;
|
||||
|
||||
sfp_init(NXP_SFP_ADDR);
|
||||
/*
|
||||
* For secure boot disable SMMU.
|
||||
* Later when platform security policy comes in picture,
|
||||
* this might get modified based on the policy
|
||||
*/
|
||||
if (check_boot_mode_secure(&mode) == true) {
|
||||
bypass_smmu(NXP_SMMU_ADDR);
|
||||
}
|
||||
|
||||
/*
|
||||
* For Mbedtls currently crypto is not supported via CAAM
|
||||
* enable it when that support is there. In tbbr.mk
|
||||
* the CAAM_INTEG is set as 0.
|
||||
*/
|
||||
|
||||
#ifndef MBEDTLS_X509
|
||||
/* Initialize the crypto accelerator if enabled */
|
||||
if (is_sec_enabled() == false) {
|
||||
INFO("SEC is disabled.\n");
|
||||
} else {
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
}
|
||||
#endif
|
||||
#elif defined(POLICY_FUSE_PROVISION)
|
||||
gpio_init(&gpio_init_data);
|
||||
sfp_init(NXP_SFP_ADDR);
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
#endif
|
||||
|
||||
soc_errata();
|
||||
|
||||
/*
|
||||
* Initialize system level generic timer for Layerscape Socs.
|
||||
*/
|
||||
delay_timer_init(NXP_TIMER_ADDR);
|
||||
|
||||
#ifdef DDR_INIT
|
||||
i2c_init(NXP_I2C_ADDR);
|
||||
dram_regions_info->total_dram_size = init_ddr();
|
||||
#endif
|
||||
}
|
||||
|
||||
void soc_bl2_prepare_exit(void)
|
||||
{
|
||||
#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
|
||||
set_sfp_wr_disable();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* This function returns the boot device based on RCW_SRC
|
||||
****************************************************************************/
|
||||
enum boot_device get_boot_dev(void)
|
||||
{
|
||||
enum boot_device src = BOOT_DEVICE_NONE;
|
||||
uint32_t porsr1;
|
||||
uint32_t rcw_src, val;
|
||||
|
||||
porsr1 = read_reg_porsr1();
|
||||
|
||||
rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
|
||||
|
||||
val = rcw_src & RCW_SRC_NAND_MASK;
|
||||
|
||||
if (val == RCW_SRC_NAND_VAL) {
|
||||
val = rcw_src & NAND_RESERVED_MASK;
|
||||
if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) {
|
||||
src = BOOT_DEVICE_IFC_NAND;
|
||||
INFO("RCW BOOT SRC is IFC NAND\n");
|
||||
}
|
||||
} else {
|
||||
/* RCW SRC NOR */
|
||||
val = rcw_src & RCW_SRC_NOR_MASK;
|
||||
if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
|
||||
src = BOOT_DEVICE_IFC_NOR;
|
||||
INFO("RCW BOOT SRC is IFC NOR\n");
|
||||
} else {
|
||||
switch (rcw_src) {
|
||||
case QSPI_VAL1:
|
||||
case QSPI_VAL2:
|
||||
src = BOOT_DEVICE_QSPI;
|
||||
INFO("RCW BOOT SRC is QSPI\n");
|
||||
break;
|
||||
case SD_VAL:
|
||||
src = BOOT_DEVICE_EMMC;
|
||||
INFO("RCW BOOT SRC is SD/EMMC\n");
|
||||
break;
|
||||
default:
|
||||
src = BOOT_DEVICE_NONE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return src;
|
||||
}
|
||||
|
||||
/* This function sets up access permissions on memory regions */
|
||||
void soc_mem_access(void)
|
||||
{
|
||||
struct tzc380_reg tzc380_reg_list[MAX_NUM_TZC_REGION];
|
||||
int dram_idx, index = 0U;
|
||||
dram_regions_info_t *info_dram_regions = get_dram_regions_info();
|
||||
|
||||
for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions;
|
||||
dram_idx++) {
|
||||
if (info_dram_regions->region[dram_idx].size == 0) {
|
||||
ERROR("DDR init failure, or");
|
||||
ERROR("DRAM regions not populated correctly.\n");
|
||||
break;
|
||||
}
|
||||
|
||||
index = populate_tzc380_reg_list(tzc380_reg_list,
|
||||
dram_idx, index,
|
||||
info_dram_regions->region[dram_idx].addr,
|
||||
info_dram_regions->region[dram_idx].size,
|
||||
NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
|
||||
}
|
||||
|
||||
mem_access_setup(NXP_TZC_ADDR, index, tzc380_reg_list);
|
||||
|
||||
/* Configure CSU secure access register to disable TZASC bypass mux */
|
||||
mmio_write_32((uintptr_t)(NXP_CSU_ADDR +
|
||||
CSU_SEC_ACCESS_REG_OFFSET),
|
||||
bswap32(TZASC_BYPASS_MUX_DISABLE));
|
||||
}
|
||||
|
||||
|
||||
#else
|
||||
const unsigned char _power_domain_tree_desc[] = {1, 1, 4};
|
||||
|
||||
CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
|
||||
assert_invalid_ls1043_cluster_count);
|
||||
|
||||
/* This function returns the SoC topology */
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
|
||||
return _power_domain_tree_desc;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function returns the core count within the cluster corresponding to
|
||||
* `mpidr`.
|
||||
*/
|
||||
unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
|
||||
{
|
||||
return CORES_PER_CLUSTER;
|
||||
}
|
||||
|
||||
void soc_early_platform_setup2(void)
|
||||
{
|
||||
dcfg_init(&dcfg_init_data);
|
||||
/* Initialize system level generic timer for Socs */
|
||||
delay_timer_init(NXP_TIMER_ADDR);
|
||||
|
||||
#if LOG_LEVEL > 0
|
||||
/* Initialize the console to provide early debug support */
|
||||
plat_console_init(NXP_CONSOLE_ADDR,
|
||||
NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* For LS1043a rev1.0, GIC base address align with 4k.
|
||||
* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
|
||||
* is set, GIC base address align with 4K, or else align
|
||||
* with 64k.
|
||||
*/
|
||||
void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base)
|
||||
{
|
||||
uint32_t *ccsr_svr = (uint32_t *)(NXP_DCFG_ADDR + DCFG_SVR_OFFSET);
|
||||
uint32_t *gic_align = (uint32_t *)(NXP_SCFG_ADDR +
|
||||
SCFG_GIC400_ADDR_ALIGN_OFFSET);
|
||||
uint32_t val;
|
||||
|
||||
val = be32toh(mmio_read_32((uintptr_t)ccsr_svr));
|
||||
|
||||
if ((val & 0xff) == REV1_1) {
|
||||
val = be32toh(mmio_read_32((uintptr_t)gic_align));
|
||||
if (val & (1L << GIC_ADDR_BIT)) {
|
||||
*gicc_base = NXP_GICC_4K_ADDR;
|
||||
*gicd_base = NXP_GICD_4K_ADDR;
|
||||
} else {
|
||||
*gicc_base = NXP_GICC_64K_ADDR;
|
||||
*gicd_base = NXP_GICD_64K_ADDR;
|
||||
}
|
||||
} else {
|
||||
*gicc_base = NXP_GICC_4K_ADDR;
|
||||
*gicd_base = NXP_GICD_4K_ADDR;
|
||||
}
|
||||
}
|
||||
|
||||
void soc_platform_setup(void)
|
||||
{
|
||||
/* Initialize the GIC driver, cpu and distributor interfaces */
|
||||
static uint32_t target_mask_array[PLATFORM_CORE_COUNT];
|
||||
/*
|
||||
* On a GICv2 system, the Group 1 secure interrupts are treated
|
||||
* as Group 0 interrupts.
|
||||
*/
|
||||
static interrupt_prop_t ls_interrupt_props[] = {
|
||||
PLAT_LS_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
|
||||
PLAT_LS_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
|
||||
};
|
||||
static uint32_t gicc_base, gicd_base;
|
||||
|
||||
get_gic_offset(&gicc_base, &gicd_base);
|
||||
plat_ls_gic_driver_init(gicd_base, gicc_base,
|
||||
PLATFORM_CORE_COUNT,
|
||||
ls_interrupt_props,
|
||||
ARRAY_SIZE(ls_interrupt_props),
|
||||
target_mask_array);
|
||||
|
||||
plat_ls_gic_init();
|
||||
enable_init_timer();
|
||||
}
|
||||
|
||||
/* This function initializes the soc from the BL31 module */
|
||||
void soc_init(void)
|
||||
{
|
||||
/* low-level init of the soc */
|
||||
soc_init_lowlevel();
|
||||
_init_global_data();
|
||||
soc_init_percpu();
|
||||
_initialize_psci();
|
||||
|
||||
/*
|
||||
* Initialize the interconnect during cold boot.
|
||||
* No need for locks as no other CPU is active.
|
||||
*/
|
||||
cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
|
||||
|
||||
/*
|
||||
* Enable coherency in interconnect for the primary CPU's cluster.
|
||||
* Earlier bootloader stages might already do this but we can't
|
||||
* assume so. No harm in executing this code twice.
|
||||
*/
|
||||
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
|
||||
|
||||
/* Init CSU to enable non-secure access to peripherals */
|
||||
enable_layerscape_ns_access(ns_dev, ARRAY_SIZE(ns_dev), NXP_CSU_ADDR);
|
||||
|
||||
/* Initialize the crypto accelerator if enabled */
|
||||
if (is_sec_enabled() == false) {
|
||||
INFO("SEC is disabled.\n");
|
||||
} else {
|
||||
sec_init(NXP_CAAM_ADDR);
|
||||
}
|
||||
}
|
||||
|
||||
void soc_runtime_setup(void)
|
||||
{
|
||||
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
#
|
||||
# Copyright 2017-2021 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# This file contains the basic architecture definitions that drive the build
|
||||
#
|
||||
# -----------------------------------------------------------------------------
|
||||
|
||||
CORE_TYPE := a53
|
||||
|
||||
CACHE_LINE := 6
|
||||
|
||||
# set to GIC400 or GIC500
|
||||
GIC := GIC400
|
||||
|
||||
# set to CCI400 or CCN504 or CCN508
|
||||
INTERCONNECT := CCI400
|
||||
|
||||
# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
|
||||
CHASSIS := 2
|
||||
|
||||
# TZC IP Details TZC used is TZC380 or TZC400
|
||||
TZC_ID := TZC380
|
||||
|
||||
# CONSOLE Details available is NS16550 or PL011
|
||||
CONSOLE := NS16550
|
||||
|
||||
# Select the DDR PHY generation to be used
|
||||
PLAT_DDR_PHY := PHY_GEN1
|
||||
|
||||
PHYS_SYS := 64
|
||||
|
||||
# ddr controller - set to MMDC or NXP
|
||||
DDRCNTLR := NXP
|
||||
|
||||
# ddr phy - set to NXP or SNPS
|
||||
DDRPHY := NXP
|
||||
|
||||
# Area of OCRAM reserved by ROM code
|
||||
NXP_ROM_RSVD := 0x5900
|
||||
|
||||
# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
|
||||
# Input to CST create_hdr_esbc tool
|
||||
CSF_HDR_SZ := 0x3000
|
||||
|
||||
# In IMAGE_BL2, compile time flag for handling Cache coherency
|
||||
# with CAAM for BL2 running from OCRAM
|
||||
SEC_MEM_NON_COHERENT := yes
|
||||
|
||||
# OCRAM MAP
|
||||
OCRAM_START_ADDR := 0x10000000
|
||||
OCRAM_SIZE := 0x20000
|
||||
|
||||
# BL2 binary is placed at start of OCRAM.
|
||||
# Also used by create_pbl.mk.
|
||||
BL2_BASE := 0x10000000
|
||||
|
||||
# After BL2 bin, OCRAM is used by ROM Code:
|
||||
# (OCRAM_START_ADDR + BL2_BIN_SIZE) -> (NXP_ROM_RSVD - 1)
|
||||
|
||||
# After ROM Code, OCRAM is used by CSF header.
|
||||
# (OCRAM_START_ADDR + BL2_TEXT_LIMIT + NXP_ROM_RSVD) -> (CSF_HDR_SZ - 1)
|
||||
|
||||
# BL2_HDR_LOC has to be (OCRAM_START_ADDR + OCRAM_SIZE - NXP_ROM_RSVD - CSF_HDR_SZ)
|
||||
# This value should be greater than BL2_TEXT_LIMIT
|
||||
# Input to CST create_hdr_isbc tool
|
||||
BL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(OCRAM_SIZE) - $(NXP_ROM_RSVD) - $(CSF_HDR_SZ))))
|
||||
# Covert to HEX to be used by create_pbl.mk
|
||||
BL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc)
|
||||
|
||||
# Core Errata
|
||||
ERRATA_A53_855873 := 1
|
||||
ERRATA_A53_1530924 := 1
|
||||
|
||||
# SoC ERRATAS to be enabled
|
||||
ERRATA_SOC_A008850 := 1
|
||||
ERRATA_SOC_A010539 := 1
|
||||
ERRATA_SOC_A009660 := 1
|
||||
|
||||
# DDR Errata
|
||||
ERRATA_DDR_A009663 := 1
|
||||
ERRATA_DDR_A009942 := 1
|
||||
|
||||
# enable dynamic memory mapping
|
||||
PLAT_XLAT_TABLES_DYNAMIC := 1
|
||||
|
||||
# Define Endianness of each module
|
||||
NXP_GUR_ENDIANNESS := BE
|
||||
NXP_DDR_ENDIANNESS := BE
|
||||
NXP_SEC_ENDIANNESS := BE
|
||||
NXP_SFP_ENDIANNESS := BE
|
||||
NXP_SNVS_ENDIANNESS := BE
|
||||
NXP_ESDHC_ENDIANNESS := BE
|
||||
NXP_QSPI_ENDIANNESS := BE
|
||||
NXP_FSPI_ENDIANNESS := BE
|
||||
NXP_SCFG_ENDIANNESS := BE
|
||||
NXP_GPIO_ENDIANNESS := BE
|
||||
NXP_IFC_ENDIANNESS := BE
|
||||
|
||||
NXP_SFP_VER := 3_2
|
||||
|
||||
# OCRAM ECC Enabled
|
||||
OCRAM_ECC_EN := yes
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
#
|
||||
# Copyright 2018-2021 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# SoC-specific build parameters
|
||||
SOC := ls1043a
|
||||
PLAT_PATH := plat/nxp
|
||||
PLAT_COMMON_PATH := plat/nxp/common
|
||||
PLAT_DRIVERS_PATH := drivers/nxp
|
||||
PLAT_SOC_PATH := ${PLAT_PATH}/soc-${SOC}
|
||||
BOARD_PATH := ${PLAT_SOC_PATH}/${BOARD}
|
||||
|
||||
# get SoC-specific defnitions
|
||||
include ${PLAT_SOC_PATH}/soc.def
|
||||
include ${PLAT_COMMON_PATH}/plat_make_helper/soc_common_def.mk
|
||||
include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
|
||||
|
||||
# For Security Features
|
||||
DISABLE_FUSE_WRITE := 1
|
||||
ifeq (${TRUSTED_BOARD_BOOT}, 1)
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
|
||||
SECURE_BOOT := yes
|
||||
endif
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,CRYPTO_NEEDED,BL_COMM))
|
||||
|
||||
# Selecting Drivers for SoC
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,DCFG_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,CSU_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,TIMER_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,INTERCONNECT_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,GIC_NEEDED,BL31))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,PMU_NEEDED,BL_COMM))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,DDR_DRIVER_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,TZASC_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,I2C_NEEDED,BL2))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
|
||||
|
||||
# Selecting PSCI & SIP_SVC support
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,PSCI_NEEDED,BL31))
|
||||
$(eval $(call SET_NXP_MAKE_FLAG,SIPSVC_NEEDED,BL31))
|
||||
|
||||
# Source File Addition
|
||||
PLAT_INCLUDES += -I${PLAT_COMMON_PATH}/include/default\
|
||||
-I${BOARD_PATH}\
|
||||
-I${PLAT_COMMON_PATH}/include/default/ch_${CHASSIS}\
|
||||
-I${PLAT_SOC_PATH}/include\
|
||||
-I${PLAT_COMMON_PATH}/soc_errata
|
||||
|
||||
ifeq (${SECURE_BOOT},yes)
|
||||
include ${PLAT_COMMON_PATH}/tbbr/tbbr.mk
|
||||
endif
|
||||
|
||||
ifeq ($(WARM_BOOT),yes)
|
||||
include ${PLAT_COMMON_PATH}/warm_reset/warm_reset.mk
|
||||
endif
|
||||
|
||||
ifeq (${NXP_NV_SW_MAINT_LAST_EXEC_DATA}, yes)
|
||||
include ${PLAT_COMMON_PATH}/nv_storage/nv_storage.mk
|
||||
endif
|
||||
|
||||
ifeq (${PSCI_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/psci/psci.mk
|
||||
endif
|
||||
|
||||
ifeq (${SIPSVC_NEEDED}, yes)
|
||||
include ${PLAT_COMMON_PATH}/sip_svc/sipsvc.mk
|
||||
endif
|
||||
|
||||
# for fuse-fip & fuse-programming
|
||||
ifeq (${FUSE_PROG}, 1)
|
||||
include ${PLAT_COMMON_PATH}/fip_handler/fuse_fip/fuse.mk
|
||||
endif
|
||||
|
||||
ifeq (${IMG_LOADR_NEEDED},yes)
|
||||
include $(PLAT_COMMON_PATH)/img_loadr/img_loadr.mk
|
||||
endif
|
||||
|
||||
# Adding source files for the above selected drivers.
|
||||
include ${PLAT_DRIVERS_PATH}/drivers.mk
|
||||
|
||||
# Adding SoC specific files
|
||||
include ${PLAT_COMMON_PATH}/soc_errata/errata.mk
|
||||
|
||||
PLAT_INCLUDES += ${NV_STORAGE_INCLUDES}\
|
||||
${WARM_RST_INCLUDES}
|
||||
|
||||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/${SOC}.S\
|
||||
${WARM_RST_BL31_SOURCES}\
|
||||
${PSCI_SOURCES}\
|
||||
${SIPSVC_SOURCES}\
|
||||
${PLAT_COMMON_PATH}/$(ARCH)/bl31_data.S
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += ${PLAT_COMMON_PATH}/$(ARCH)/ls_helpers.S\
|
||||
${PLAT_SOC_PATH}/aarch64/${SOC}_helpers.S\
|
||||
${NV_STORAGE_SOURCES}\
|
||||
${WARM_RST_BL_COMM_SOURCES}\
|
||||
${PLAT_SOC_PATH}/soc.c
|
||||
|
||||
ifeq (${TEST_BL31}, 1)
|
||||
BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/bootmain64.S\
|
||||
${PLAT_SOC_PATH}/$(ARCH)/nonboot64.S
|
||||
endif
|
||||
|
||||
BL2_SOURCES += ${DDR_CNTLR_SOURCES}\
|
||||
${TBBR_SOURCES}\
|
||||
${FUSE_SOURCES}
|
||||
|
||||
# Adding TFA setup files
|
||||
include ${PLAT_PATH}/common/setup/common.mk
|
||||
Loading…
Reference in New Issue