andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge pull request #1139 from hzhuang1/fix_edmac 

Fix edmac
This commit is contained in:
davidcunado-arm 2017-10-23 16:45:59 +01:00 committed by GitHub
parent 4c37ac8903 454748fc86
commit 3b39efa49d
3 changed files with 35 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
plat/hisilicon/hikey/hikey_bl1_setup.c
View File

@ -489,6 +489,15 @@ static void hikey_mmc_pll_init(void)
reset_mmc1_clk();
}
static void hikey_rtc_init(void)
{
uint32_t data;
data = mmio_read_32(AO_SC_PERIPH_CLKEN4);
data |= AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N;
mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
}
/*
* Function which will perform any remaining platform-specific setup that can
* occur after the MMU and data cache have been enabled.
@ -505,6 +514,8 @@ void bl1_platform_setup(void)
hikey_pmussi_init();
hikey_hi6553_init();
hikey_rtc_init();
hikey_mmc_pll_init();
memset(&params, 0, sizeof(dw_mmc_params_t));

17
plat/hisilicon/hikey/hikey_bl31_setup.c
View File

@ -16,6 +16,7 @@
#include <hi6220.h>
#include <hisi_ipc.h>
#include <hisi_pwrc.h>
#include <mmio.h>
#include <platform_def.h>
#include "hikey_def.h"
@ -152,6 +153,20 @@ void bl31_plat_arch_setup(void)
BL31_COHERENT_RAM_LIMIT);
}
/* Initialize EDMAC controller with non-secure mode. */
static void hikey_edma_init(void)
{
int i;
uint32_t non_secure;
non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC;
mmio_write_32(EDMAC_SEC_CTRL, non_secure);
for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) {
mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18));
}
}
void bl31_platform_setup(void)
{
/* Initialize the GIC driver, cpu and distributor interfaces */
@ -160,6 +175,8 @@ void bl31_platform_setup(void)
gicv2_pcpu_distif_init();
gicv2_cpuif_enable();
hikey_edma_init();
hisi_ipc_init();
hisi_pwrc_setup();
}

7
plat/hisilicon/hikey/include/hi6220.h
View File

@ -42,6 +42,13 @@
#define DWUSB_BASE 0xF72C0000
#define EDMAC_BASE 0xf7370000
#define EDMAC_SEC_CTRL (EDMAC_BASE + 0x694)
#define EDMAC_AXI_CONF(x) (EDMAC_BASE + 0x820 + (x << 6))
#define EDMAC_SEC_CTRL_INTR_SEC (1 << 1)
#define EDMAC_SEC_CTRL_GLOBAL_SEC (1 << 0)
#define EDMAC_CHANNEL_NUMS 16
#define PMUSSI_BASE 0xF8000000
#define SP804_TIMER0_BASE 0xF8008000