hikey: Add BL32 (OP-TEE) support
Signed-off-by: Victor Chong <victor.chong@linaro.org>
This commit is contained in:
Victor Chong
parent
c0cde3640a
commit
3b6e88a2b3
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@ -14,6 +14,9 @@ Code Locations
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- ARM Trusted Firmware:
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`link <https://github.com/ARM-software/arm-trusted-firmware>`__
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- OP-TEE
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`link <https://github.com/OP-TEE/optee_os>`__
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- edk2:
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`link <https://github.com/96boards-hikey/edk2/tree/testing/hikey960_v2.5>`__
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@ -70,7 +73,7 @@ Build Procedure
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FASTBOOT_BUILD_OPTION=$(echo ${BUILD_OPTION} | tr '[A-Z]' '[a-z]')
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cd ${EDK2_DIR}
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# Build UEFI & ARM Trust Firmware
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${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware hikey
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${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey
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# Generate l-loader.bin
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cd ${BUILD_PATH}/l-loader
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ln -sf ${EDK2_OUTPUT_DIR}/FV/bl1.bin
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@ -24,6 +24,10 @@
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DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
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TSP_SEC_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_ROM_PARAM MAP_REGION_FLAT(XG2RAM0_BASE, \
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BL1_XG2RAM0_OFFSET, \
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MT_DEVICE | MT_RO | MT_SECURE)
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@ -59,6 +63,7 @@ static const mmap_region_t hikey_mmap[] = {
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static const mmap_region_t hikey_mmap[] = {
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MAP_DDR,
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MAP_DEVICE,
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MAP_TSP_MEM,
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{0}
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};
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#endif
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@ -67,6 +72,15 @@ static const mmap_region_t hikey_mmap[] = {
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static const mmap_region_t hikey_mmap[] = {
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MAP_DEVICE,
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MAP_SRAM,
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MAP_TSP_MEM,
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{0}
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};
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#endif
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#if IMAGE_BL32
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static const mmap_region_t hikey_mmap[] = {
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MAP_DEVICE,
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MAP_DDR,
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{0}
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};
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#endif
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@ -144,6 +144,41 @@ void bl2_plat_set_bl31_ep_info(image_info_t *image,
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DISABLE_ALL_EXCEPTIONS);
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}
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/*******************************************************************************
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* Before calling this function BL32 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL32 and set SPSR and security state.
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* On Hikey we only set the security state of the entrypoint
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******************************************************************************/
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#ifdef BL32_BASE
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void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
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entry_point_info_t *bl32_ep_info)
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{
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SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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bl32_ep_info->spsr = 0;
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}
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/*******************************************************************************
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* Populate the extents of memory available for loading BL32
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******************************************************************************/
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void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
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{
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/*
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* Populate the extents of memory available for loading BL32.
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*/
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bl32_meminfo->total_base = BL32_BASE;
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bl32_meminfo->free_base = BL32_BASE;
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bl32_meminfo->total_size =
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(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
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bl32_meminfo->free_size =
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(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
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}
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#endif /* BL32_BASE */
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void bl2_plat_set_bl33_ep_info(image_info_t *image,
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entry_point_info_t *bl33_ep_info)
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{
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@ -20,6 +20,25 @@
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#define XG2RAM0_BASE 0xF9800000
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#define XG2RAM0_SIZE 0x00400000
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/* Memory location options for TSP */
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#define HIKEY_SRAM_ID 0
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#define HIKEY_DRAM_ID 1
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/*
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* DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
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* regions
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* - Secure DDR (default is the top 16MB) used by OP-TEE
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* - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
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* - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
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* - Non-secure DDR (8MB) reserved for OP-TEE's future use
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*/
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#define DDR_SEC_SIZE 0x01000000
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#define DDR_SEC_BASE (DDR_BASE + DDR_SIZE - DDR_SEC_SIZE)
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#define DDR_SDP_SIZE 0x00400000
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#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
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DDR_SDP_SIZE)
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#define SRAM_BASE 0xFFF80000
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#define SRAM_SIZE 0x00012000
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@ -73,6 +73,10 @@ static const io_uuid_spec_t bl31_uuid_spec = {
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.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
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};
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static const io_uuid_spec_t bl32_uuid_spec = {
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.uuid = UUID_SECURE_PAYLOAD_BL32,
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};
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static const io_uuid_spec_t bl33_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
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};
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@ -102,6 +106,11 @@ static const struct plat_io_policy policies[] = {
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(uintptr_t)&bl31_uuid_spec,
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check_fip
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},
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[BL32_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl32_uuid_spec,
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check_fip
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},
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[BL33_IMAGE_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl33_uuid_spec,
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@ -97,6 +97,33 @@
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#define BL31_BASE BL2_LIMIT
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#define BL31_LIMIT 0xF9898000
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/*
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* BL3-2 specific defines.
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*/
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/*
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* The TSP currently executes from TZC secured area of DRAM or SRAM.
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*/
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#define BL32_SRAM_BASE BL31_LIMIT
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#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
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#define BL32_DRAM_BASE DDR_SEC_BASE
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#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
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#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
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#define BL32_BASE BL32_DRAM_BASE
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#define BL32_LIMIT BL32_DRAM_LIMIT
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#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
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#define BL32_BASE BL32_SRAM_BASE
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#define BL32_LIMIT BL32_SRAM_LIMIT
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#else
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#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
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#endif
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#define NS_BL1U_BASE (BL2_BASE)
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#define NS_BL1U_SIZE (0x00010000)
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#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
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@ -106,10 +133,14 @@
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*/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL31
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#if IMAGE_BL1 || IMAGE_BL2 || IMAGE_BL32
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#define MAX_XLAT_TABLES 3
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#endif
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#if IMAGE_BL31
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#define MAX_XLAT_TABLES 4
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#endif
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#define MAX_MMAP_REGIONS 16
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#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
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@ -4,6 +4,17 @@
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# On Hikey, the TSP can execute from TZC secure area in DRAM (default)
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# or SRAM.
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HIKEY_TSP_RAM_LOCATION := dram
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ifeq (${HIKEY_TSP_RAM_LOCATION}, dram)
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HIKEY_TSP_RAM_LOCATION_ID = HIKEY_DRAM_ID
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else ifeq (${HIKEY_TSP_RAM_LOCATION}, sram)
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HIKEY_TSP_RAM_LOCATION_ID := HIKEY_SRAM_ID
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else
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$(error "Currently unsupported HIKEY_TSP_RAM_LOCATION value")
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endif
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CONSOLE_BASE := PL011_UART3_BASE
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CRASH_CONSOLE_BASE := PL011_UART3_BASE
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PLAT_PARTITION_MAX_ENTRIES := 12
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@ -12,6 +23,7 @@ COLD_BOOT_SINGLE_CPU := 1
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PROGRAMMABLE_RESET_ADDRESS := 1
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# Process flags
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$(eval $(call add_define,HIKEY_TSP_RAM_LOCATION_ID))
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$(eval $(call add_define,CONSOLE_BASE))
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$(eval $(call add_define,CRASH_CONSOLE_BASE))
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$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
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