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feat(plat/mdeiatek/mt8195): add DFD control in SiP service 

DFD (Design for Debug) is a debugging tool, which scans
flip-flops and dumps to internal RAM on the WDT reset.
After system reboots, those values could be showed for
debugging.

BUG=b:192429713

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I02c6c862b6217bc84c83a09b533bd53ec19b06f7
This commit is contained in:
Rex-BC Chen 2021-08-10 11:10:58 +08:00
parent c7c22ab662
commit 3b994a7530
7 changed files with 259 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

156
plat/mediatek/mt8195/drivers/dfd/plat_dfd.c Normal file
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@ -0,0 +1,156 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <mtk_sip_svc.h>
#include <plat_dfd.h>
static bool dfd_enabled;
static uint64_t dfd_base_addr;
static uint64_t dfd_chain_length;
static uint64_t dfd_cache_dump;
static void dfd_setup(uint64_t base_addr, uint64_t chain_length,
uint64_t cache_dump)
{
mmio_write_32(MTK_WDT_LATCH_CTL2, MTK_WDT_LATCH_CTL2_VAL);
mmio_write_32(MTK_WDT_INTERVAL, MTK_WDT_INTERVAL_VAL);
mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_VAL);
mmio_write_32(MTK_DRM_LATCH_CTL1, MTK_DRM_LATCH_CTL1_VAL);
/* Bit[2] = 0 (default=1), disable dfd apb bus protect_en */
mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, 0x1 << 2);
/* Bit[0] : enable?mcusys_vproc?external_off?dfd?trigger -> 1 */
mmio_setbits_32(DFD_V50_GROUP_0_63_DIFF, 0x1);
/* bit[0]: rg_rw_dfd_internal_dump_en -> 1 */
/* bit[2]: rg_rw_dfd_clock_stop_en -> 1 */
sync_writel(DFD_INTERNAL_CTL, 0x5);
/* bit[13]: xreset_b_update_disable */
mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13);
/*
* bit[10:3]: DFD trigger selection mask
* bit[3]: rg_rw_dfd_trigger_sel[0] = 1(enable wdt trigger)
* bit[4]: rg_rw_dfd_trigger_sel[1] = 1(enable HW trigger)
* bit[5]: rg_rw_dfd_trigger_sel[2] = 1(enable SW trigger)
* bit[6]: rg_rw_dfd_trigger_sel[3] = 1(enable SW non-security trigger)
* bit[7]: rg_rw_dfd_trigger_sel[4] = 1(enable timer trigger)
*/
mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3);
/*
* bit[9] : rg_rw_dfd_trigger_sel[6] = 1(cpu_eb_sw_dfd_trigger)
* bit[10] : rg_rw_dfd_trigger_sel[7] = 1(cpu_eb_wdt_dfd_trigger)
*/
mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9);
/* bit[20:19]: rg_dfd_armpll_div_mux_sel switch to PLL2 for DFD */
mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19);
/*
* bit[0]: rg_rw_dfd_auto_power_on = 1
* bit[2:1]: rg_rw_dfd_auto_power_on_dely = 1(10us)
* bit[4:2]: rg_rw_dfd_power_on_wait_time = 1(20us)
*/
mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB);
/* longest scan chain length */
mmio_write_32(DFD_CHAIN_LENGTH0, chain_length);
/* bit[1:0]: rg_rw_dfd_shift_clock_ratio */
mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0);
/* rg_dfd_test_so_over_64 */
mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1);
/* DFD3.0 */
mmio_write_32(DFD_TEST_SI_0, 0x0);
mmio_write_32(DFD_TEST_SI_1, 0x0);
mmio_write_32(DFD_TEST_SI_2, 0x0);
mmio_write_32(DFD_TEST_SI_3, 0x0);
/* for iLDO feature */
sync_writel(DFD_POWER_CTL, 0xF9);
/* read offset */
sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL);
/* for DFD-3.0 setup */
sync_writel(DFD_V30_CTL, 0xD);
/* set base address */
mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24);
mmio_write_32(DFD_O_REG_0, 0);
/* setup global variables for suspend and resume */
dfd_enabled = true;
dfd_base_addr = base_addr;
dfd_chain_length = chain_length;
dfd_cache_dump = cache_dump;
if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
mmio_write_32(MTK_DRM_LATCH_CTL2, MTK_DRM_LATCH_CTL2_CACHE_VAL);
sync_writel(DFD_V35_ENABLE, 0x1);
sync_writel(DFD_V35_TAP_NUMBER, 0xB);
sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
/* Cache dump only mode */
sync_writel(DFD_V35_CTL, 0x1);
mmio_write_32(DFD_INTERNAL_NUM_OF_TEST_SO_GROUP, 0xF);
mmio_write_32(DFD_CHAIN_LENGTH0, DFD_CHAIN_LENGTH_VAL);
mmio_write_32(DFD_CHAIN_LENGTH1, DFD_CHAIN_LENGTH_VAL);
mmio_write_32(DFD_CHAIN_LENGTH2, DFD_CHAIN_LENGTH_VAL);
mmio_write_32(DFD_CHAIN_LENGTH3, DFD_CHAIN_LENGTH_VAL);
if ((cache_dump & DFD_PARITY_ERR_TRIGGER) != 0UL) {
sync_writel(DFD_HW_TRIGGER_MASK, 0xC);
mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4);
}
}
dsbsy();
}
void dfd_resume(void)
{
if (dfd_enabled == true) {
dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
}
}
uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
uint64_t arg2, uint64_t arg3)
{
uint64_t ret = 0L;
switch (arg0) {
case PLAT_MTK_DFD_SETUP_MAGIC:
INFO("[%s] DFD setup call from kernel\n", __func__);
dfd_setup(arg1, arg2, arg3);
break;
case PLAT_MTK_DFD_READ_MAGIC:
/* only allow to access DFD register base + 0x200 */
if (arg1 <= 0x200) {
ret = mmio_read_32(MISC1_CFG_BASE + arg1);
}
break;
case PLAT_MTK_DFD_WRITE_MAGIC:
/* only allow to access DFD register base + 0x200 */
if (arg1 <= 0x200) {
sync_writel(MISC1_CFG_BASE + arg1, arg2);
}
break;
default:
ret = MTK_SIP_E_INVALID_PARAM;
break;
}
return ret;
}

85
plat/mediatek/mt8195/drivers/dfd/plat_dfd.h Normal file
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@ -0,0 +1,85 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_DFD_H
#define PLAT_DFD_H
#include <arch_helpers.h>
#include <lib/mmio.h>
#include <platform_def.h>
#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \
dsbsy(); \
} while (0)
#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150)
#define PLAT_MTK_DFD_READ_MAGIC (0x99716151)
#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152)
#define MTK_DRM_LATCH_CTL1 (DRM_BASE + 0x40)
#define MTK_DRM_LATCH_CTL2 (DRM_BASE + 0x44)
#define MTK_WDT_BASE (RGU_BASE)
#define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x10)
#define MTK_WDT_LATCH_CTL2 (MTK_WDT_BASE + 0x48)
#define MCU_BIU_BASE (MCUCFG_BASE)
#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040)
#define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)
#define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)
#define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)
#define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)
#define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)
#define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20)
#define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24)
#define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)
#define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)
#define DFD_INTERNAL_TEST_SO_OVER_64 (MISC1_CFG_BASE + 0x34)
#define DFD_INTERNAL_SW_NS_TRIGGER (MISC1_CFG_BASE + 0x3c)
#define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)
#define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C)
#define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50)
#define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)
#define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)
#define DFD_CLEAN_STATUS (MISC1_CFG_BASE + 0x60)
#define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8)
#define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC)
#define DFD_READ_ADDR (MISC1_CFG_BASE + 0x1E8)
#define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC)
#define DFD_V35_ENABLE (MCU_BIU_BASE + 0xE0A8)
#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC)
#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0)
#define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4)
#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0)
#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4)
#define DFD_V50_GROUP_0_63_DIFF (MCU_BIU_BASE + 0xE2AC)
#define DFD_O_PROTECT_EN_REG (0x10001220)
#define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C)
#define DFD_O_SET_BASEADDR_REG (0x10043000)
#define DFD_O_REG_0 (0x10001390)
#define DFD_CACHE_DUMP_ENABLE 1U
#define DFD_PARITY_ERR_TRIGGER 2U
#define DFD_V35_TAP_EN_VAL (0x43FF)
#define DFD_V35_SEQ0_0_VAL (0x63668820)
#define DFD_READ_ADDR_VAL (0x40000008)
#define DFD_CHAIN_LENGTH_VAL (0xFFFFFFFF)
#define MTK_WDT_LATCH_CTL2_VAL (0x9507FFFF)
#define MTK_WDT_INTERVAL_VAL (0x6600000A)
#define MTK_DRM_LATCH_CTL2_VAL (0x950600C8)
#define MTK_DRM_LATCH_CTL2_CACHE_VAL (0x95065DC0)
#define MTK_DRM_LATCH_CTL1_VAL (0x95000013)
void dfd_resume(void);
uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
uint64_t arg2, uint64_t arg3);
#endif /* PLAT_DFD_H */

6
plat/mediatek/mt8195/include/plat_sip_calls.h
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@ -10,7 +10,11 @@
/*******************************************************************************
* Plat SiP function constants
******************************************************************************/
#define MTK_PLAT_SIP_NUM_CALLS 2
#define MTK_PLAT_SIP_NUM_CALLS 4
/* DFD */
#define MTK_SIP_KERNEL_DFD_AARCH32 0x82000205
#define MTK_SIP_KERNEL_DFD_AARCH64 0xC2000205
/* DP/eDP */
#define MTK_SIP_DP_CONTROL_AARCH32 0x82000523

2
plat/mediatek/mt8195/include/platform_def.h
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@ -24,7 +24,9 @@
#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
#define SPM_BASE (IO_PHYS + 0x00006000)
#define RGU_BASE (IO_PHYS + 0x00007000)
#define APMIXEDSYS (IO_PHYS + 0x0000C000)
#define DRM_BASE (IO_PHYS + 0x0000D000)
#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000)
#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
#define VPPSYS0_BASE (IO_PHYS + 0x04000000)

3
plat/mediatek/mt8195/plat_pm.c
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@ -17,6 +17,7 @@
#include <mtk_ptp3_common.h>
#include <mtspmc.h>
#include <plat/common/platform.h>
#include <plat_dfd.h>
#include <plat_mtk_lpm.h>
#include <plat_params.h>
#include <plat_pm.h>
@ -166,6 +167,8 @@ static void plat_mcusys_pwron_common(unsigned int cpu,
mt_gic_distif_restore();
gic_sgi_restore_all();
dfd_resume();
plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state);
}

6
plat/mediatek/mt8195/plat_sip_calls.c
View File

@ -10,6 +10,7 @@
#include <mt_spm.h>
#include <mt_spm_vcorefs.h>
#include <mtk_sip_svc.h>
#include <plat_dfd.h>
#include "plat_sip_calls.h"
uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
@ -35,6 +36,11 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
ret = spm_vcorefs_v2_args(x1, x2, x3, &x4);
SMC_RET2(handle, ret, x4);
break;
case MTK_SIP_KERNEL_DFD_AARCH32:
case MTK_SIP_KERNEL_DFD_AARCH64:
ret = dfd_smc_dispatcher(x1, x2, x3, x4);
SMC_RET1(handle, ret);
break;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;

2
plat/mediatek/mt8195/platform.mk
View File

@ -15,6 +15,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT}/common/drivers/uart/ \
-I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT_SOC}/drivers/dcm \
-I${MTK_PLAT_SOC}/drivers/dfd \
-I${MTK_PLAT_SOC}/drivers/dp/ \
-I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
@ -60,6 +61,7 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
${MTK_PLAT_SOC}/drivers/dfd/plat_dfd.c \
${MTK_PLAT_SOC}/drivers/dp/mt_dp.c \
${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \