AArch32: Refactor SP_MIN to support RESET_TO_SP_MIN
This patch uses the `el3_entrypoint_common` macro to initialize CPU registers, in SP_MIN entrypoint.s file, in both cold and warm boot path. It also adds conditional compilation, in cold and warm boot entry path, based on RESET_TO_SP_MIN. Change-Id: Id493ca840dc7b9e26948dc78ee928e9fdb76b9e4
This commit is contained in:
Yatharth Kochar
parent
6fe8aa2fa6
commit
3bdf0e5df2
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@ -32,6 +32,7 @@
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <context.h>
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#include <el3_common_macros.S>
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#include <runtime_svc.h>
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#include <smcc_helpers.h>
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#include <smcc_macros.S>
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@ -41,7 +42,8 @@
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.globl sp_min_entrypoint
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.globl sp_min_warm_entrypoint
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func sp_min_vector_table
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vector_base sp_min_vector_table
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b sp_min_entrypoint
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b plat_panic_handler /* Undef */
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b handle_smc /* Syscall */
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@ -50,185 +52,70 @@ func sp_min_vector_table
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b plat_panic_handler /* Reserved */
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b plat_panic_handler /* IRQ */
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b plat_panic_handler /* FIQ */
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endfunc sp_min_vector_table
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func handle_smc
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smcc_save_gp_mode_regs
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/* r0 points to smc_context */
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mov r2, r0 /* handle */
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ldcopr r0, SCR
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/* Save SCR in stack */
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push {r0}
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and r3, r0, #SCR_NS_BIT /* flags */
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/* Switch to Secure Mode*/
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bic r0, #SCR_NS_BIT
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stcopr r0, SCR
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isb
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ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */
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/* Check whether an SMC64 is issued */
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tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT)
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beq 1f /* SMC32 is detected */
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mov r0, #SMC_UNK
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str r0, [r2, #SMC_CTX_GPREG_R0]
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mov r0, r2
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b 2f /* Skip handling the SMC */
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1:
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mov r1, #0 /* cookie */
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bl handle_runtime_svc
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2:
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/* r0 points to smc context */
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/* Restore SCR from stack */
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pop {r1}
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stcopr r1, SCR
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isb
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b sp_min_exit
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endfunc handle_smc
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/*
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* The Cold boot/Reset entrypoint for SP_MIN
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*/
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func sp_min_entrypoint
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/*
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* The caches and TLBs are disabled at reset. If any implementation
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* allows the caches/TLB to be hit while they are disabled, ensure
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* that they are invalidated here
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#if !RESET_TO_SP_MIN
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/* ---------------------------------------------------------------
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* Preceding bootloader has populated r0 with a pointer to a
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* 'bl_params_t' structure & r1 with a pointer to platform
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* specific structure
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* ---------------------------------------------------------------
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*/
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mov r11, r0
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mov r12, r1
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/* Make sure we are in Secure Mode*/
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ldcopr r0, SCR
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bic r0, #SCR_NS_BIT
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stcopr r0, SCR
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isb
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/* Switch to monitor mode */
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cps #MODE32_mon
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isb
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/*
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* Set sane values for NS SCTLR as well.
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* Switch to non secure mode for this.
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/* ---------------------------------------------------------------------
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* For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
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* sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
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* and primary/secondary CPU logic should not be executed in this case.
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*
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* Also, assume that the previous bootloader has already set up the CPU
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* endianness and has initialised the memory.
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* ---------------------------------------------------------------------
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*/
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ldr r0, =(SCTLR_RES1)
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ldcopr r1, SCR
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orr r2, r1, #SCR_NS_BIT
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stcopr r2, SCR
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isb
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el3_entrypoint_common \
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_set_endian=0 \
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_warm_boot_mailbox=0 \
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_secondary_cold_boot=0 \
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_init_memory=0 \
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_init_c_runtime=1 \
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_exception_vectors=sp_min_vector_table
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ldcopr r2, SCTLR
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orr r0, r0, r2
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stcopr r0, SCTLR
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isb
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stcopr r1, SCR
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isb
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/*
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* Set the CPU endianness before doing anything that might involve
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* memory reads or writes.
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/* ---------------------------------------------------------------------
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* Relay the previous bootloader's arguments to the platform layer
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* ---------------------------------------------------------------------
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*/
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ldcopr r0, SCTLR
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bic r0, r0, #SCTLR_EE_BIT
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stcopr r0, SCTLR
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isb
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/* Run the CPU Specific Reset handler */
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bl reset_handler
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/*
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* Enable the instruction cache and data access
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* alignment checks
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mov r0, r11
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mov r1, r12
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#else
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/* ---------------------------------------------------------------------
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* For RESET_TO_SP_MIN systems which have a programmable reset address,
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* sp_min_entrypoint() is executed only on the cold boot path so we can
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* skip the warm boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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ldcopr r0, SCTLR
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ldr r1, =(SCTLR_RES1 | SCTLR_A_BIT | SCTLR_I_BIT)
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orr r0, r0, r1
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stcopr r0, SCTLR
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isb
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el3_entrypoint_common \
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_set_endian=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=sp_min_vector_table
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/* Set the vector tables */
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ldr r0, =sp_min_vector_table
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stcopr r0, VBAR
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stcopr r0, MVBAR
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isb
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/*
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* Enable the SIF bit to disable instruction fetches
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* from Non-secure memory.
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/* ---------------------------------------------------------------------
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* For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
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* to run so there's no argument to relay from a previous bootloader.
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* Zero the arguments passed to the platform layer to reflect that.
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* ---------------------------------------------------------------------
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*/
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ldcopr r0, SCR
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orr r0, r0, #SCR_SIF_BIT
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stcopr r0, SCR
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mov r0, #0
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mov r1, #0
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#endif /* RESET_TO_SP_MIN */
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/*
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* Enable the SError interrupt now that the exception vectors have been
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* setup.
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*/
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cpsie a
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isb
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/* Enable access to Advanced SIMD registers */
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ldcopr r0, NSACR
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bic r0, r0, #NSASEDIS_BIT
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orr r0, r0, #(NASCR_CP10_BIT | NASCR_CP11_BIT)
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stcopr r0, NSACR
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isb
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/*
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* Enable access to Advanced SIMD, Floating point and to the Trace
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* functionality as well.
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*/
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ldcopr r0, CPACR
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bic r0, r0, #ASEDIS_BIT
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bic r0, r0, #TRCDIS_BIT
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orr r0, r0, #CPACR_ENABLE_FP_ACCESS
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stcopr r0, CPACR
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isb
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vmrs r0, FPEXC
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orr r0, r0, #FPEXC_EN_BIT
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vmsr FPEXC, r0
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/* Detect whether Warm or Cold boot */
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bl plat_get_my_entrypoint
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cmp r0, #0
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/* If warm boot detected, jump to warm boot entry */
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bxne r0
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/* Setup C runtime stack */
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bl plat_set_my_stack
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/* Perform platform specific memory initialization */
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bl platform_mem_init
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/* Initialize the C Runtime Environment */
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/*
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* Invalidate the RW memory used by SP_MIN image. This includes
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* the data and NOBITS sections. This is done to safeguard against
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* possible corruption of this memory by dirty cache lines in a system
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* cache as a result of use by an earlier boot loader stage.
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*/
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ldr r0, =__RW_START__
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ldr r1, =__RW_END__
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sub r1, r1, r0
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bl inv_dcache_range
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ldr r0, =__BSS_START__
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ldr r1, =__BSS_SIZE__
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bl zeromem
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#if USE_COHERENT_MEM
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ldr r0, =__COHERENT_RAM_START__
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ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem
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#endif
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/* Perform platform specific early arch. setup */
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bl sp_min_early_platform_setup
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bl sp_min_plat_arch_setup
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@ -270,13 +157,76 @@ func sp_min_entrypoint
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b sp_min_exit
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endfunc sp_min_entrypoint
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/*
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* SMC handling function for SP_MIN.
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*/
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func handle_smc
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smcc_save_gp_mode_regs
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/* r0 points to smc_context */
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mov r2, r0 /* handle */
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ldcopr r0, SCR
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/* Save SCR in stack */
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push {r0}
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and r3, r0, #SCR_NS_BIT /* flags */
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/* Switch to Secure Mode*/
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bic r0, #SCR_NS_BIT
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stcopr r0, SCR
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isb
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ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */
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/* Check whether an SMC64 is issued */
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tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT)
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beq 1f /* SMC32 is detected */
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mov r0, #SMC_UNK
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str r0, [r2, #SMC_CTX_GPREG_R0]
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mov r0, r2
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b 2f /* Skip handling the SMC */
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1:
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mov r1, #0 /* cookie */
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bl handle_runtime_svc
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2:
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/* r0 points to smc context */
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/* Restore SCR from stack */
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pop {r1}
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stcopr r1, SCR
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isb
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b sp_min_exit
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endfunc handle_smc
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/*
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* The Warm boot entrypoint for SP_MIN.
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*/
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func sp_min_warm_entrypoint
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/* Setup C runtime stack */
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bl plat_set_my_stack
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/*
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* On the warm boot path, most of the EL3 initialisations performed by
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* 'el3_entrypoint_common' must be skipped:
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*
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* - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by
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* programming the reset address do we need to set the CPU endianness.
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* In other cases, we assume this has been taken care by the
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* entrypoint code.
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*
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* - No need to determine the type of boot, we know it is a warm boot.
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*
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* - Do not try to distinguish between primary and secondary CPUs, this
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* notion only exists for a cold boot.
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*
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* - No need to initialise the memory or the C runtime environment,
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* it has been done once and for all on the cold boot path.
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*/
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el3_entrypoint_common \
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_set_endian=PROGRAMMABLE_RESET_ADDRESS \
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_warm_boot_mailbox=0 \
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_secondary_cold_boot=0 \
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_init_memory=0 \
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_init_c_runtime=0 \
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_exception_vectors=sp_min_vector_table
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/* --------------------------------------------
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* Enable the MMU with the DCache disabled. It
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@ -50,6 +50,7 @@ SECTIONS
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__TEXT_START__ = .;
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*entrypoint.o(.text*)
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*(.text*)
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*(.vectors)
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. = NEXT(4096);
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__TEXT_END__ = .;
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} >RAM
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@ -98,6 +99,7 @@ SECTIONS
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KEEP(*(cpu_ops))
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__CPU_OPS_END__ = .;
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*(.vectors)
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__RO_END_UNALIGNED__ = .;
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/*
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