Merge pull request #1403 from glneo/for-upstream-k3
TI K3 platform support
This commit is contained in:
Dimitris Papastamos
GitHub
commit
3caa841d9c
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@ -0,0 +1,55 @@
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Trusted Firmware-A for Texas Instruments K3 SoCs
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================================================
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Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Texas Instruments K3 SoCs.
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Boot Flow
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---------
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R5(U-Boot) --> TF-A BL31 --> BL32(OP-TEE) --> TF-A BL31 --> BL33(U-Boot) --> Linux
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\
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Optional direct to Linux boot
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\
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--> BL33(Linux)
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Texas Instruments K3 SoCs contain an R5 processor used as the boot master, it
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loads the needed images for A53 startup, because of this we do not need BL1 or
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BL2 TF-A stages.
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Build Instructions
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------------------
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https://github.com/ARM-software/arm-trusted-firmware.git
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TF-A:
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.. code:: shell
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make CROSS_COMPILE=aarch64-linux-gnu- PLAT=k3 SPD=opteed all
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OP-TEE:
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.. code:: shell
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make ARCH=arm CROSS_COMPILE64=aarch64-linux-gnu- PLATFORM=k3 CFG_ARM64_core=y all
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R5 U-Boot:
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.. code:: shell
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make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- am65x_evm_r5_defconfig
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make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- SYSFW=<path to SYSFW>
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A53 U-Boot:
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.. code:: shell
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make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- am65x_evm_a53_defconfig
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make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path> TEE=<path>
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Deploy Images
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-------------
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.. code:: shell
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cp tiboot3.bin tispl.bin u-boot.img /sdcard/boot/
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@ -132,6 +132,16 @@ Files:
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- plat/rockchip/\*
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Texas Instruments platform sub-maintainer
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-----------------------------------------
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Andrew F. Davis (afd@ti.com, `glneo`_)
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Files:
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- docs/plat/ti-k3.rst
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- plat/ti/\*
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UniPhier platform sub-maintainer
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--------------------------------
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@ -167,6 +177,7 @@ Etienne Carriere (etienne.carriere@linaro.org, `etienne-lms`_)
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.. _masahir0y: https://github.com/masahir0y
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.. _mtk09422: https://github.com/mtk09422
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.. _TonyXie06: https://github.com/TonyXie06
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.. _glneo: https://github.com/glneo
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.. _sivadur: https://github.com/sivadur
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.. _rockchip-linux: https://github.com/rockchip-linux
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.. _etienne-lms: https://github.com/etienne-lms
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#
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# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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BL32_BASE ?= 0x9e800000
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$(eval $(call add_define,BL32_BASE))
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PRELOADED_BL33_BASE ?= 0x80080000
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$(eval $(call add_define,PRELOADED_BL33_BASE))
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K3_HW_CONFIG_BASE ?= 0x82000000
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$(eval $(call add_define,K3_HW_CONFIG_BASE))
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PLAT_INCLUDES += \
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-Iplat/ti/k3/board/generic/include \
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@ -0,0 +1,33 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __BOARD_DEF_H__
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#define __BOARD_DEF_H__
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/* The ports must be in order and contiguous */
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#define K3_CLUSTER0_CORE_COUNT 2
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#define K3_CLUSTER0_MSMC_PORT 0
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#define K3_CLUSTER1_CORE_COUNT 2
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#define K3_CLUSTER1_MSMC_PORT 1
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#define K3_CLUSTER2_CORE_COUNT 2
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#define K3_CLUSTER2_MSMC_PORT 2
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#define K3_CLUSTER3_CORE_COUNT 2
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#define K3_CLUSTER3_MSMC_PORT 3
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/*
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* This RAM will be used for the bootloader including code, bss, and stacks.
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* It may need to be increased if BL31 grows in size.
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*/
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#define SEC_SRAM_BASE 0x70000000 /* Base of MSMC SRAM */
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#define SEC_SRAM_SIZE 0x00020000 /* 128k */
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#define PLAT_MAX_OFF_STATE 2
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#define PLAT_MAX_RET_STATE 1
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#endif /* __BOARD_DEF_H__ */
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <k3_console.h>
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#include <plat_arm.h>
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#include <platform_def.h>
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#include <k3_gicv3.h>
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#include <string.h>
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/* Table of regions to map using the MMU */
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const mmap_region_t plat_arm_mmap[] = {
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MAP_REGION_FLAT(SHARED_RAM_BASE, SHARED_RAM_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(K3_USART_BASE_ADDRESS, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(K3_GICD_BASE, K3_GICD_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(K3_GICR_BASE, K3_GICR_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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{ /* sentinel */ }
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};
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/*
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* Placeholder variables for maintaining information about the next image(s)
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*/
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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static uint32_t k3_get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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/*******************************************************************************
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* Perform any BL3-1 early platform setup, such as console init and deciding on
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* memory layout.
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******************************************************************************/
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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{
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/* There are no parameters from BL2 if BL31 is a reset vector */
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assert(from_bl2 == NULL);
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assert(plat_params_from_bl2 == NULL);
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bl31_console_setup();
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#ifdef BL32_BASE
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/* Populate entry point information for BL32 */
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SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
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#endif
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/* Populate entry point information for BL33 */
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SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
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bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
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bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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#ifdef K3_HW_CONFIG_BASE
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/*
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* According to the file ``Documentation/arm64/booting.txt`` of the
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* Linux kernel tree, Linux expects the physical address of the device
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* tree blob (DTB) in x0, while x1-x3 are reserved for future use and
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* must be 0.
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*/
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bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE;
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bl33_image_ep_info.args.arg1 = 0U;
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bl33_image_ep_info.args.arg2 = 0U;
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bl33_image_ep_info.args.arg3 = 0U;
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#endif
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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bl31_early_platform_setup((void *)arg0, (void *)arg1);
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}
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void bl31_plat_arch_setup(void)
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{
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arm_setup_page_tables(BL31_BASE,
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BL31_END - BL31_BASE,
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BL_CODE_BASE,
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BL_CODE_END,
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BL_RO_DATA_BASE,
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BL_RO_DATA_END);
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enable_mmu_el3(0);
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}
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void bl31_platform_setup(void)
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{
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k3_gic_driver_init(K3_GICD_BASE, K3_GICR_BASE);
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k3_gic_init();
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}
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void platform_mem_init(void)
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{
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/* Do nothing for now... */
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return SYS_COUNTER_FREQ_IN_TICKS;
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}
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/*
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* Empty function to prevent the console from being uninitialized after BL33 is
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* started and allow us to see messages from BL31.
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*/
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void bl31_plat_runtime_setup(void)
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{
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}
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image
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* for the security state specified. BL3-3 corresponds to the non-secure
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* image type while BL3-2 corresponds to the secure image type. A NULL
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* pointer is returned if the image does not exist.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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assert(sec_state_is_valid(type));
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next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info :
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&bl32_image_ep_info;
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/*
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* None of the images on the ARM development platforms can have 0x0
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* as the entrypoint
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*/
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if (next_image_info->pc)
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return next_image_info;
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NOTICE("Requested nonexistent image\n");
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return NULL;
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}
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <console.h>
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#include <k3_console.h>
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#include <platform_def.h>
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#include <uart_16550.h>
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void bl31_console_setup(void)
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{
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static console_16550_t console;
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/* Initialize the console to provide early debug support */
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console_16550_register(K3_USART_BASE_ADDRESS, K3_USART_CLK_SPEED,
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K3_USART_BAUD, &console);
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}
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <bl_common.h>
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#include <gicv3.h>
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#include <interrupt_props.h>
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#include <k3_gicv3.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <utils.h>
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/* The GICv3 driver only needs to be initialized in EL3 */
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uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static const interrupt_prop_t k3_interrupt_props[] = {
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PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
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PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
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};
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static unsigned int k3_mpidr_to_core_pos(unsigned long mpidr)
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{
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return (unsigned int)plat_core_pos_by_mpidr(mpidr);
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}
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gicv3_driver_data_t k3_gic_data = {
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.interrupt_props = k3_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(k3_interrupt_props),
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.mpidr_to_core_pos = k3_mpidr_to_core_pos,
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};
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void k3_gic_driver_init(uintptr_t gicd_base, uintptr_t gicr_base)
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{
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/*
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* The GICv3 driver is initialized in EL3 and does not need
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* to be initialized again in SEL1. This is because the S-EL1
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* can use GIC system registers to manage interrupts and does
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* not need GIC interface base addresses to be configured.
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*/
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k3_gic_data.gicd_base = gicd_base;
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k3_gic_data.gicr_base = gicr_base;
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gicv3_driver_init(&k3_gic_data);
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}
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void k3_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void k3_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void k3_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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void k3_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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#define K3_BOOT_REASON_COLD_RESET 0x1
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/* ------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint(void)
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* ------------------------------------------------------------------
|
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*
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* This function is called with the called with the MMU and caches
|
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* disabled (SCTLR_EL3.M = 0 and SCTLR_EL3.C = 0). The function is
|
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* responsible for distinguishing between a warm and cold reset for the
|
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* current CPU using platform-specific means. If it's a warm reset,
|
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* then it returns the warm reset entrypoint point provided to
|
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* plat_setup_psci_ops() during BL31 initialization. If it's a cold
|
||||
* reset then this function must return zero.
|
||||
*
|
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* This function does not follow the Procedure Call Standard used by
|
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* the Application Binary Interface for the ARM 64-bit architecture.
|
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* The caller should not assume that callee saved registers are
|
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* preserved across a call to this function.
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*/
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.globl plat_get_my_entrypoint
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func plat_get_my_entrypoint
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ldr x0, k3_boot_reason_data_store
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cmp x0, #K3_BOOT_REASON_COLD_RESET
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|
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/* We ONLY support cold boot at this point */
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bne plat_unsupported_boot
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mov x0, #0
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ret
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|
||||
/*
|
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* We self manage our boot reason.
|
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* At load time, we have just a default reason - which is cold reset
|
||||
*/
|
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k3_boot_reason_data_store:
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.word K3_BOOT_REASON_COLD_RESET
|
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|
||||
plat_unsupported_boot:
|
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b plat_unsupported_boot
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|
||||
endfunc plat_get_my_entrypoint
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|
||||
/* ------------------------------------------------------------------
|
||||
* unsigned int plat_my_core_pos(void)
|
||||
* ------------------------------------------------------------------
|
||||
*
|
||||
* This function returns the index of the calling CPU which is used as a
|
||||
* CPU-specific linear index into blocks of memory (for example while
|
||||
* allocating per-CPU stacks). This function will be invoked very early
|
||||
* in the initialization sequence which mandates that this function
|
||||
* should be implemented in assembly and should not rely on the
|
||||
* avalability of a C runtime environment. This function can clobber x0
|
||||
* - x8 and must preserve x9 - x29.
|
||||
*
|
||||
* This function plays a crucial role in the power domain topology
|
||||
* framework in PSCI and details of this can be found in Power Domain
|
||||
* Topology Design.
|
||||
*/
|
||||
.globl plat_my_core_pos
|
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func plat_my_core_pos
|
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mrs x0, MPIDR_EL1
|
||||
|
||||
and x1, x0, #MPIDR_CLUSTER_MASK
|
||||
lsr x1, x1, #MPIDR_AFF1_SHIFT
|
||||
and x0, x0, #MPIDR_CPU_MASK
|
||||
|
||||
#if K3_CLUSTER1_MSMC_PORT != UNUSED
|
||||
cmp x1, #K3_CLUSTER0_MSMC_PORT
|
||||
b.eq out
|
||||
add x0, x0, #K3_CLUSTER0_CORE_COUNT
|
||||
#if K3_CLUSTER2_MSMC_PORT != UNUSED
|
||||
cmp x1, #K3_CLUSTER1_MSMC_PORT
|
||||
b.eq out
|
||||
add x0, x0, #K3_CLUSTER1_CORE_COUNT
|
||||
#if K3_CLUSTER3_MSMC_PORT != UNUSED
|
||||
cmp x1, #K3_CLUSTER2_MSMC_PORT
|
||||
b.eq out
|
||||
add x0, x0, #K3_CLUSTER2_CORE_COUNT
|
||||
#endif /* K3_CLUSTER3_MSMC_PORT != UNUSED */
|
||||
#endif /* K3_CLUSTER2_MSMC_PORT != UNUSED */
|
||||
#endif /* K3_CLUSTER1_MSMC_PORT != UNUSED */
|
||||
|
||||
out:
|
||||
ret
|
||||
endfunc plat_my_core_pos
|
||||
|
||||
/* ---------------------------------------------
|
||||
* int plat_crash_console_init(void)
|
||||
* Function to initialize the crash console
|
||||
* without a C Runtime to print crash report.
|
||||
* Clobber list : x0 - x4
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func plat_crash_console_init
|
||||
mov_imm x0, CRASH_CONSOLE_BASE
|
||||
mov_imm x1, CRASH_CONSOLE_CLK
|
||||
mov_imm x2, CRASH_CONSOLE_BAUD_RATE
|
||||
mov w3, #0x0
|
||||
b console_core_init
|
||||
|
||||
endfunc plat_crash_console_init
|
||||
|
||||
/* ---------------------------------------------
|
||||
* int plat_crash_console_putc(void)
|
||||
* Function to print a character on the crash
|
||||
* console without a C Runtime.
|
||||
* Clobber list : x1, x2
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
func plat_crash_console_putc
|
||||
mov_imm x1, CRASH_CONSOLE_BASE
|
||||
b console_core_putc
|
||||
endfunc plat_crash_console_putc
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
#include <k3_gicv3.h>
|
||||
#include <psci.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#define STUB() ERROR("stub %s called\n", __func__)
|
||||
|
||||
uintptr_t k3_sec_entrypoint;
|
||||
|
||||
static void k3_cpu_standby(plat_local_state_t cpu_state)
|
||||
{
|
||||
/*
|
||||
* Enter standby state
|
||||
* dsb is good practice before using wfi to enter low power states
|
||||
*/
|
||||
dsb();
|
||||
wfi();
|
||||
}
|
||||
|
||||
static int k3_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
sev();
|
||||
|
||||
/* TODO: Indicate to System firmware about powering up */
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
void k3_pwr_domain_off(const psci_power_state_t *target_state)
|
||||
{
|
||||
/* Prevent interrupts from spuriously waking up this cpu */
|
||||
k3_gic_cpuif_disable();
|
||||
|
||||
/* TODO: Indicate to System firmware about powering down */
|
||||
}
|
||||
|
||||
void k3_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
/* TODO: Indicate to System firmware about completion */
|
||||
|
||||
k3_gic_pcpu_init();
|
||||
k3_gic_cpuif_enable();
|
||||
}
|
||||
|
||||
static void __dead2 k3_system_reset(void)
|
||||
{
|
||||
/* TODO: Indicate to System firmware about system reset */
|
||||
STUB();
|
||||
|
||||
while (true)
|
||||
wfi();
|
||||
}
|
||||
|
||||
static int k3_validate_power_state(unsigned int power_state,
|
||||
psci_power_state_t *req_state)
|
||||
{
|
||||
/* TODO: perform the proper validation */
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static int k3_validate_ns_entrypoint(uintptr_t entrypoint)
|
||||
{
|
||||
/* TODO: perform the proper validation */
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static const plat_psci_ops_t k3_plat_psci_ops = {
|
||||
.cpu_standby = k3_cpu_standby,
|
||||
.pwr_domain_on = k3_pwr_domain_on,
|
||||
.pwr_domain_off = k3_pwr_domain_off,
|
||||
.pwr_domain_on_finish = k3_pwr_domain_on_finish,
|
||||
.system_reset = k3_system_reset,
|
||||
.validate_power_state = k3_validate_power_state,
|
||||
.validate_ns_entrypoint = k3_validate_ns_entrypoint
|
||||
};
|
||||
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
k3_sec_entrypoint = sec_entrypoint;
|
||||
|
||||
*psci_ops = &k3_plat_psci_ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
#include <psci.h>
|
||||
|
||||
/* The power domain tree descriptor */
|
||||
static unsigned char power_domain_tree_desc[] = {
|
||||
PLATFORM_CLUSTER_COUNT,
|
||||
K3_CLUSTER0_CORE_COUNT,
|
||||
#if K3_CLUSTER1_MSMC_PORT != UNUSED
|
||||
K3_CLUSTER1_CORE_COUNT,
|
||||
#endif /* K3_CLUSTER1_MSMC_PORT != UNUSED */
|
||||
#if K3_CLUSTER2_MSMC_PORT != UNUSED
|
||||
K3_CLUSTER2_CORE_COUNT,
|
||||
#endif /* K3_CLUSTER2_MSMC_PORT != UNUSED */
|
||||
#if K3_CLUSTER3_MSMC_PORT != UNUSED
|
||||
K3_CLUSTER3_CORE_COUNT,
|
||||
#endif /* K3_CLUSTER3_MSMC_PORT != UNUSED */
|
||||
};
|
||||
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
return power_domain_tree_desc;
|
||||
}
|
||||
|
||||
int plat_core_pos_by_mpidr(u_register_t mpidr)
|
||||
{
|
||||
unsigned int cpu_id;
|
||||
|
||||
mpidr &= MPIDR_AFFINITY_MASK;
|
||||
|
||||
if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
|
||||
return -1;
|
||||
|
||||
cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
|
||||
switch (MPIDR_AFFLVL1_VAL(mpidr)) {
|
||||
case K3_CLUSTER0_MSMC_PORT:
|
||||
if (cpu_id < K3_CLUSTER0_CORE_COUNT)
|
||||
return cpu_id;
|
||||
return -1;
|
||||
#if K3_CLUSTER1_MSMC_PORT != UNUSED
|
||||
case K3_CLUSTER1_MSMC_PORT:
|
||||
if (cpu_id < K3_CLUSTER1_CORE_COUNT)
|
||||
return K3_CLUSTER0_CORE_COUNT + cpu_id;
|
||||
return -1;
|
||||
#endif /* K3_CLUSTER1_MSMC_PORT != UNUSED */
|
||||
#if K3_CLUSTER2_MSMC_PORT != UNUSED
|
||||
case K3_CLUSTER2_MSMC_PORT:
|
||||
if (cpu_id < K3_CLUSTER2_CORE_COUNT)
|
||||
return K3_CLUSTER0_CORE_COUNT +
|
||||
K3_CLUSTER1_CORE_COUNT + cpu_id;
|
||||
return -1;
|
||||
#endif /* K3_CLUSTER2_MSMC_PORT != UNUSED */
|
||||
#if K3_CLUSTER3_MSMC_PORT != UNUSED
|
||||
case K3_CLUSTER3_MSMC_PORT:
|
||||
if (cpu_id < K3_CLUSTER3_CORE_COUNT)
|
||||
return K3_CLUSTER0_CORE_COUNT +
|
||||
K3_CLUSTER1_CORE_COUNT +
|
||||
K3_CLUSTER2_CORE_COUNT + cpu_id;
|
||||
return -1;
|
||||
#endif /* K3_CLUSTER3_MSMC_PORT != UNUSED */
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
#
|
||||
# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
# We don't use BL1 or BL2, so BL31 is the first image to execute
|
||||
RESET_TO_BL31 := 1
|
||||
# Only one core starts up at first
|
||||
COLD_BOOT_SINGLE_CPU := 1
|
||||
# We can choose where a core starts executing
|
||||
PROGRAMMABLE_RESET_ADDRESS:= 1
|
||||
|
||||
# System coherency is managed in hardware
|
||||
HW_ASSISTED_COHERENCY := 1
|
||||
USE_COHERENT_MEM := 0
|
||||
|
||||
ERROR_DEPRECATED := 1
|
||||
ENABLE_PLAT_COMPAT := 0
|
||||
|
||||
# A53 erratum for SoC. (enable them all)
|
||||
ERRATA_A53_826319 := 1
|
||||
ERRATA_A53_835769 := 1
|
||||
ERRATA_A53_836870 := 1
|
||||
ERRATA_A53_843419 := 1
|
||||
ERRATA_A53_855873 := 1
|
||||
|
||||
MULTI_CONSOLE_API := 1
|
||||
TI_16550_MDR_QUIRK := 1
|
||||
$(eval $(call add_define,TI_16550_MDR_QUIRK))
|
||||
|
||||
# Libraries
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
||||
PLAT_INCLUDES += \
|
||||
-I${PLAT_PATH}/include \
|
||||
-Iinclude/plat/arm/common/ \
|
||||
-Iinclude/plat/arm/common/aarch64/ \
|
||||
|
||||
K3_CONSOLE_SOURCES += \
|
||||
drivers/console/aarch64/console.S \
|
||||
drivers/ti/uart/aarch64/16550_console.S \
|
||||
${PLAT_PATH}/common/k3_console.c \
|
||||
|
||||
K3_GIC_SOURCES += \
|
||||
drivers/arm/gic/common/gic_common.c \
|
||||
drivers/arm/gic/v3/gicv3_main.c \
|
||||
drivers/arm/gic/v3/gicv3_helpers.c \
|
||||
plat/common/plat_gicv3.c \
|
||||
${PLAT_PATH}/common/k3_gicv3.c \
|
||||
|
||||
K3_PSCI_SOURCES += \
|
||||
plat/common/plat_psci_common.c \
|
||||
${PLAT_PATH}/common/k3_psci.c \
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += \
|
||||
plat/arm/common/arm_common.c \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
${XLAT_TABLES_LIB_SRCS} \
|
||||
${K3_CONSOLE_SOURCES} \
|
||||
|
||||
BL31_SOURCES += \
|
||||
${PLAT_PATH}/common/k3_bl31_setup.c \
|
||||
${PLAT_PATH}/common/k3_helpers.S \
|
||||
${PLAT_PATH}/common/k3_topology.c \
|
||||
${K3_GIC_SOURCES} \
|
||||
${K3_PSCI_SOURCES} \
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __K3_CONSOLE_H__
|
||||
#define __K3_CONSOLE_H__
|
||||
|
||||
void bl31_console_setup(void);
|
||||
|
||||
#endif /* __K3_CONSOLE_H__ */
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __K3_GICV3_H__
|
||||
#define __K3_GICV3_H__
|
||||
|
||||
void k3_gic_driver_init(uintptr_t gicd_base, uintptr_t gicr_base);
|
||||
void k3_gic_init(void);
|
||||
void k3_gic_cpuif_enable(void);
|
||||
void k3_gic_cpuif_disable(void);
|
||||
void k3_gic_pcpu_init(void);
|
||||
|
||||
#endif /* __K3_GICV3_H__ */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_MACROS_S__
|
||||
#define __PLAT_MACROS_S__
|
||||
|
||||
/* ---------------------------------------------
|
||||
* The below required platform porting macro
|
||||
* prints out relevant platform registers
|
||||
* whenever an unhandled exception is taken in
|
||||
* BL31.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.macro plat_crash_print_regs
|
||||
/* STUB */
|
||||
.endm
|
||||
|
||||
#endif /* __PLAT_MACROS_S__ */
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __PLATFORM_DEF_H__
|
||||
#define __PLATFORM_DEF_H__
|
||||
|
||||
#include <arch.h>
|
||||
#include <board_def.h>
|
||||
#include <common_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Generic platform constants
|
||||
******************************************************************************/
|
||||
|
||||
/* Size of cacheable stack */
|
||||
#if IMAGE_BL31
|
||||
#define PLATFORM_STACK_SIZE 0x800
|
||||
#else
|
||||
#define PLATFORM_STACK_SIZE 0x1000
|
||||
#endif
|
||||
|
||||
#define PLATFORM_SYSTEM_COUNT 1
|
||||
#define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \
|
||||
K3_CLUSTER1_CORE_COUNT + \
|
||||
K3_CLUSTER2_CORE_COUNT + \
|
||||
K3_CLUSTER3_CORE_COUNT)
|
||||
|
||||
#define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_MSMC_PORT != UNUSED) + \
|
||||
(K3_CLUSTER1_MSMC_PORT != UNUSED) + \
|
||||
(K3_CLUSTER2_MSMC_PORT != UNUSED) + \
|
||||
(K3_CLUSTER3_MSMC_PORT != UNUSED))
|
||||
|
||||
#define UNUSED -1
|
||||
|
||||
#if !defined(K3_CLUSTER1_CORE_COUNT) || !defined(K3_CLUSTER1_MSMC_PORT)
|
||||
#define K3_CLUSTER1_CORE_COUNT 0
|
||||
#define K3_CLUSTER1_MSMC_PORT UNUSED
|
||||
#endif
|
||||
|
||||
#if !defined(K3_CLUSTER2_CORE_COUNT) || !defined(K3_CLUSTER2_MSMC_PORT)
|
||||
#define K3_CLUSTER2_CORE_COUNT 0
|
||||
#define K3_CLUSTER2_MSMC_PORT UNUSED
|
||||
#endif
|
||||
|
||||
#if !defined(K3_CLUSTER3_CORE_COUNT) || !defined(K3_CLUSTER3_MSMC_PORT)
|
||||
#define K3_CLUSTER3_CORE_COUNT 0
|
||||
#define K3_CLUSTER3_MSMC_PORT UNUSED
|
||||
#endif
|
||||
|
||||
#if K3_CLUSTER0_MSMC_PORT == UNUSED
|
||||
#error "ARM cluster 0 must be used"
|
||||
#endif
|
||||
|
||||
#if ((K3_CLUSTER1_MSMC_PORT == UNUSED) && (K3_CLUSTER1_CORE_COUNT != 0)) || \
|
||||
((K3_CLUSTER2_MSMC_PORT == UNUSED) && (K3_CLUSTER2_CORE_COUNT != 0)) || \
|
||||
((K3_CLUSTER3_MSMC_PORT == UNUSED) && (K3_CLUSTER3_CORE_COUNT != 0))
|
||||
#error "Unused ports must have 0 ARM cores"
|
||||
#endif
|
||||
|
||||
#define PLATFORM_CLUSTER_OFFSET K3_CLUSTER0_MSMC_PORT
|
||||
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
|
||||
PLATFORM_CORE_COUNT)
|
||||
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory layout constants
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* ARM-TF lives in SRAM, partition it here
|
||||
*/
|
||||
|
||||
#define SHARED_RAM_BASE BL31_LIMIT
|
||||
#define SHARED_RAM_SIZE 0x00001000
|
||||
|
||||
/*
|
||||
* BL3-1 specific defines.
|
||||
*
|
||||
* Put BL3-1 at the base of the Trusted SRAM, before SHARED_RAM.
|
||||
*/
|
||||
#define BL31_BASE SEC_SRAM_BASE
|
||||
#define BL31_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE)
|
||||
#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
|
||||
#define BL31_PROGBITS_LIMIT BL31_LIMIT
|
||||
|
||||
/*
|
||||
* Defines the maximum number of translation tables that are allocated by the
|
||||
* translation table library code. To minimize the amount of runtime memory
|
||||
* used, choose the smallest value needed to map the required virtual addresses
|
||||
* for each BL stage.
|
||||
*/
|
||||
#define MAX_XLAT_TABLES 8
|
||||
|
||||
/*
|
||||
* Defines the maximum number of regions that are allocated by the translation
|
||||
* table library code. A region consists of physical base address, virtual base
|
||||
* address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
|
||||
* defined in the `mmap_region_t` structure. The platform defines the regions
|
||||
* that should be mapped. Then, the translation table library will create the
|
||||
* corresponding tables and descriptors at runtime. To minimize the amount of
|
||||
* runtime memory used, choose the smallest value needed to register the
|
||||
* required regions for each BL stage.
|
||||
*/
|
||||
#define MAX_MMAP_REGIONS 8
|
||||
|
||||
/*
|
||||
* Defines the total size of the address space in bytes. For example, for a 32
|
||||
* bit address space, this value should be `(1ull << 32)`.
|
||||
*/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
|
||||
|
||||
/*
|
||||
* Some data must be aligned on the biggest cache line size in the platform.
|
||||
* This is known only to the platform as it might have a combination of
|
||||
* integrated and external caches.
|
||||
*/
|
||||
#define CACHE_WRITEBACK_SHIFT 6
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
/* Platform default console definitions */
|
||||
#ifndef K3_USART_BASE_ADDRESS
|
||||
#define K3_USART_BASE_ADDRESS 0x02800000
|
||||
#endif
|
||||
|
||||
/* USART has a default size for address space */
|
||||
#define K3_USART_SIZE 0x1000
|
||||
|
||||
#ifndef K3_USART_CLK_SPEED
|
||||
#define K3_USART_CLK_SPEED 48000000
|
||||
#endif
|
||||
|
||||
#ifndef K3_USART_BAUD
|
||||
#define K3_USART_BAUD 115200
|
||||
#endif
|
||||
|
||||
/* Crash console defaults */
|
||||
#define CRASH_CONSOLE_BASE K3_USART_BASE_ADDRESS
|
||||
#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
|
||||
#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
|
||||
|
||||
/* Timer frequency */
|
||||
#ifndef SYS_COUNTER_FREQ_IN_TICKS
|
||||
#define SYS_COUNTER_FREQ_IN_TICKS 200000000
|
||||
#endif
|
||||
|
||||
/* Interrupt numbers */
|
||||
#define ARM_IRQ_SEC_PHY_TIMER 29
|
||||
|
||||
#define ARM_IRQ_SEC_SGI_0 8
|
||||
#define ARM_IRQ_SEC_SGI_1 9
|
||||
#define ARM_IRQ_SEC_SGI_2 10
|
||||
#define ARM_IRQ_SEC_SGI_3 11
|
||||
#define ARM_IRQ_SEC_SGI_4 12
|
||||
#define ARM_IRQ_SEC_SGI_5 13
|
||||
#define ARM_IRQ_SEC_SGI_6 14
|
||||
#define ARM_IRQ_SEC_SGI_7 15
|
||||
|
||||
/*
|
||||
* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
|
||||
* terminology. On a GICv2 system or mode, the lists will be merged and treated
|
||||
* as Group 0 interrupts.
|
||||
*/
|
||||
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE)
|
||||
|
||||
#define PLAT_ARM_G0_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE), \
|
||||
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_EDGE)
|
||||
|
||||
#define K3_GICD_BASE 0x01800000
|
||||
#define K3_GICD_SIZE 0x10000
|
||||
#define K3_GICR_BASE 0x01880000
|
||||
#define K3_GICR_SIZE 0x100000
|
||||
|
||||
#endif /* __PLATFORM_DEF_H__ */
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#
|
||||
# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
PLAT_PATH := plat/ti/k3
|
||||
TARGET_BOARD ?= generic
|
||||
|
||||
include ${PLAT_PATH}/common/plat_common.mk
|
||||
include ${PLAT_PATH}/board/${TARGET_BOARD}/board.mk
|
||||
|
||||
# modify BUILD_PLAT to point to board specific build directory
|
||||
BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_BOARD}/${BUILD_TYPE}
|
||||
|
|
@ -183,6 +183,7 @@ This release also contains the following platform support:
|
|||
- Raspberry Pi 3 board
|
||||
- RockChip RK3328, RK3368 and RK3399 SoCs
|
||||
- Socionext UniPhier SoC family
|
||||
- Texas Instruments K3 SoCs
|
||||
- Xilinx Zynq UltraScale + MPSoC
|
||||
|
||||
Still to come
|
||||
|
|
|
|||
Loading…
Reference in New Issue