Enable AMU for Cortex-Hercules
Change-Id: Ie0a94783d0c8e111ae19fd592304e6485f04ca29 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
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@ -22,4 +22,20 @@
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#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
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#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30)
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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******************************************************************************/
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#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
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#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
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#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
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#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
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#define CORTEX_HERCULES_AMU_GROUP0_MASK U(0xF)
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#define CORTEX_HERCULES_AMU_GROUP1_MASK U(0x7)
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#endif /* CORTEX_HERCULES_H */
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#endif /* CORTEX_HERCULES_H */
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@ -14,6 +14,35 @@
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/* Hardware handled coherency */
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled"
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#error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-Hercules
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* -------------------------------------------------
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*/
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#if ENABLE_AMU
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func cortex_hercules_reset_func
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
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msr actlr_el3, x0
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/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
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msr actlr_el2, x0
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/* Enable group0 counters */
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mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK
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msr CPUAMCNTENSET0_EL0, x0
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/* Enable group1 counters */
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mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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isb
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ret
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endfunc cortex_hercules_reset_func
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#endif
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#endif
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/* ---------------------------------------------
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/* ---------------------------------------------
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@ -60,6 +89,12 @@ func cortex_hercules_cpu_reg_dump
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ret
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ret
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endfunc cortex_hercules_cpu_reg_dump
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endfunc cortex_hercules_cpu_reg_dump
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#if ENABLE_AMU
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#define HERCULES_RESET_FUNC cortex_hercules_reset_func
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#else
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#define HERCULES_RESET_FUNC CPU_NO_RESET_FUNC
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#endif
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declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \
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declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \
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CPU_NO_RESET_FUNC, \
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HERCULES_RESET_FUNC, \
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cortex_hercules_core_pwr_dwn
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cortex_hercules_core_pwr_dwn
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