From 3d14a30b88762e901e134acc89c6ac4fa9e3f321 Mon Sep 17 00:00:00 2001
From: Jiafei Pan <Jiafei.Pan@nxp.com>
Date: Thu, 21 Oct 2021 16:57:58 +0800
Subject: [PATCH] feat(nxp/common/errata): add SoC erratum a008850

Add SoC erratum a008850 support.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I1ef41c67737b7b5fdf1d892929a2d8040effc282
---
 plat/nxp/common/soc_errata/errata.c         |  4 ++
 plat/nxp/common/soc_errata/errata.h         |  2 +
 plat/nxp/common/soc_errata/errata.mk        |  3 +-
 plat/nxp/common/soc_errata/errata_a008850.c | 42 +++++++++++++++++++++
 plat/nxp/common/soc_errata/errata_list.h    |  5 +++
 5 files changed, 55 insertions(+), 1 deletion(-)
 create mode 100644 plat/nxp/common/soc_errata/errata_a008850.c

diff --git a/plat/nxp/common/soc_errata/errata.c b/plat/nxp/common/soc_errata/errata.c
index fb1818a85..a117c9165 100644
--- a/plat/nxp/common/soc_errata/errata.c
+++ b/plat/nxp/common/soc_errata/errata.c
@@ -14,6 +14,10 @@ void soc_errata(void)
 #ifdef ERRATA_SOC_A050426
 	INFO("SoC workaround for Errata A050426 was applied\n");
 	erratum_a050426();
+#endif
+#ifdef ERRATA_SOC_A008850
+	INFO("SoC workaround for Errata A008850 Early-Phase was applied\n");
+	erratum_a008850_early();
 #endif
 	/*
 	 * The following DDR Erratas workaround are implemented in DDR driver,
diff --git a/plat/nxp/common/soc_errata/errata.h b/plat/nxp/common/soc_errata/errata.h
index b543b4bb9..ab679957d 100644
--- a/plat/nxp/common/soc_errata/errata.h
+++ b/plat/nxp/common/soc_errata/errata.h
@@ -8,6 +8,8 @@
 #ifndef ERRATA_H
 #define ERRATA_H
 
+#include "errata_list.h"
+
 void soc_errata(void);
 
 #endif /* ERRATA_H */
diff --git a/plat/nxp/common/soc_errata/errata.mk b/plat/nxp/common/soc_errata/errata.mk
index 294261531..d2511bbb3 100644
--- a/plat/nxp/common/soc_errata/errata.mk
+++ b/plat/nxp/common/soc_errata/errata.mk
@@ -8,7 +8,8 @@
 # applied.
 
 ERRATA := \
-  ERRATA_SOC_A050426
+  ERRATA_SOC_A050426 \
+  ERRATA_SOC_A008850
 
 define enable_errata
   $(1) ?= 0
diff --git a/plat/nxp/common/soc_errata/errata_a008850.c b/plat/nxp/common/soc_errata/errata_a008850.c
new file mode 100644
index 000000000..e8c0f6408
--- /dev/null
+++ b/plat/nxp/common/soc_errata/errata_a008850.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include <cci.h>
+#include <common/debug.h>
+#include <ls_interconnect.h>
+#include <mmio.h>
+
+#include <platform_def.h>
+
+void erratum_a008850_early(void)
+{
+	/* part 1 of 2 */
+	uintptr_t cci_base = NXP_CCI_ADDR;
+	uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG);
+
+	/* enabling forced barrier termination on CCI400 */
+	mmio_write_32(cci_base + CTRL_OVERRIDE_REG,
+		      (val | CCI_TERMINATE_BARRIER_TX));
+
+}
+
+void erratum_a008850_post(void)
+{
+	/* part 2 of 2 */
+	uintptr_t cci_base = NXP_CCI_ADDR;
+	uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG);
+
+	/* Clear the BARRIER_TX bit */
+	val = val & ~(CCI_TERMINATE_BARRIER_TX);
+
+	/*
+	 * Disable barrier termination on CCI400, allowing
+	 * barriers to propagate across CCI
+	 */
+	mmio_write_32(cci_base + CTRL_OVERRIDE_REG, val);
+
+	INFO("SoC workaround for Errata A008850 Post-Phase was applied\n");
+}
diff --git a/plat/nxp/common/soc_errata/errata_list.h b/plat/nxp/common/soc_errata/errata_list.h
index 74d23150d..ae95fa203 100644
--- a/plat/nxp/common/soc_errata/errata_list.h
+++ b/plat/nxp/common/soc_errata/errata_list.h
@@ -12,4 +12,9 @@
 void erratum_a050426(void);
 #endif
 
+#ifdef ERRATA_SOC_A008850
+void erratum_a008850_early(void);
+void erratum_a008850_post(void);
+#endif
+
 #endif /* ERRATA_LIST_H */