From 3e28e9354013452674ad191634da0dab2f5c460d Mon Sep 17 00:00:00 2001 From: Jeetesh Burman Date: Mon, 22 Jan 2018 15:40:08 +0530 Subject: [PATCH] Tegra: SiP: set GPU in reset after vpr resize Whenever the VPR memory is resized, the GPU is put into reset first and then the new VPR parameters are programmed to the memory controller block. There exists a scenario, where the GPU might be out before we program the new VPR parameters. This means, the GPU would still be using older settings and leak secrets. This patch puts the GPU back into reset, if it is out of reset after resizing VPR, to mitigate this hole. Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931 Signed-off-by: Jeetesh Burman --- plat/nvidia/tegra/common/tegra_sip_calls.c | 10 ++++++++++ plat/nvidia/tegra/include/t132/tegra_def.h | 2 ++ plat/nvidia/tegra/include/t186/tegra_def.h | 2 ++ plat/nvidia/tegra/include/t210/tegra_def.h | 2 ++ 4 files changed, 16 insertions(+) diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/common/tegra_sip_calls.c index 4955b2fc1..957300e53 100644 --- a/plat/nvidia/tegra/common/tegra_sip_calls.c +++ b/plat/nvidia/tegra/common/tegra_sip_calls.c @@ -116,6 +116,16 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid, /* new video memory carveout settings */ tegra_memctrl_videomem_setup(x1, local_x2_32); + /* + * Ensure again that GPU is still in reset after VPR resize + */ + regval = mmio_read_32(TEGRA_CAR_RESET_BASE + + TEGRA_GPU_RESET_REG_OFFSET); + if ((regval & GPU_RESET_BIT) == 0U) { + mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_GPU_SET_OFFSET, + GPU_SET_BIT); + } + SMC_RET1(handle, 0); /* diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h index fd75fbce6..2fe321b22 100644 --- a/plat/nvidia/tegra/include/t132/tegra_def.h +++ b/plat/nvidia/tegra/include/t132/tegra_def.h @@ -41,7 +41,9 @@ ******************************************************************************/ #define TEGRA_CAR_RESET_BASE U(0x60006000) #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) +#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290) #define GPU_RESET_BIT (U(1) << 24) +#define GPU_SET_BIT (U(1) << 24) /******************************************************************************* * Tegra Flow Controller constants diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index 231f93ac8..2603ccb2a 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -210,7 +210,9 @@ ******************************************************************************/ #define TEGRA_CAR_RESET_BASE U(0x05000000) #define TEGRA_GPU_RESET_REG_OFFSET U(0x30) +#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x34) #define GPU_RESET_BIT (U(1) << 0) +#define GPU_SET_BIT (U(1) << 0) #define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index 75919e11e..0285867af 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -85,7 +85,9 @@ ******************************************************************************/ #define TEGRA_CAR_RESET_BASE U(0x60006000) #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) +#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290) #define GPU_RESET_BIT (U(1) << 24) +#define GPU_SET_BIT (U(1) << 24) #define TEGRA_RST_DEV_CLR_V U(0x434) #define TEGRA_CLK_ENB_V U(0x440)