AArch32: Add SMCC context
This patch defines a SMCC context to save and restore registers during a SMC call. It also adds appropriate helpers to save and restore from this context for use by AArch32 secure payload and BL stages. Change-Id: I64c8d6fe1d6cac22e1f1f39ea1b54ee1b1b72248
This commit is contained in:
Soby Mathew
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1ae0a49a37
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3e3616ab21
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SMCC_HELPERS_H__
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#define __SMCC_HELPERS_H__
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#include <smcc.h>
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/* These are offsets to registers in smc_ctx_t */
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#define SMC_CTX_GPREG_R0 0x0
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#define SMC_CTX_GPREG_R1 0x4
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#define SMC_CTX_GPREG_R2 0x8
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#define SMC_CTX_GPREG_R3 0xC
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#define SMC_CTX_GPREG_R4 0x10
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#define SMC_CTX_SP_USR 0x34
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#define SMC_CTX_SPSR_MON 0x78
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#define SMC_CTX_LR_MON 0x7C
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#define SMC_CTX_SIZE 0x80
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#ifndef __ASSEMBLY__
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#include <cassert.h>
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#include <types.h>
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/*
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* The generic structure to save arguments and callee saved registers during
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* an SMC. Also this structure is used to store the result return values after
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* the completion of SMC service.
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*/
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typedef struct smc_ctx {
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u_register_t r0;
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u_register_t r1;
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u_register_t r2;
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u_register_t r3;
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u_register_t r4;
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u_register_t r5;
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u_register_t r6;
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u_register_t r7;
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u_register_t r8;
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u_register_t r9;
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u_register_t r10;
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u_register_t r11;
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u_register_t r12;
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/* spsr_usr doesn't exist */
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u_register_t sp_usr;
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u_register_t lr_usr;
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u_register_t spsr_irq;
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u_register_t sp_irq;
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u_register_t lr_irq;
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u_register_t spsr_fiq;
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u_register_t sp_fiq;
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u_register_t lr_fiq;
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u_register_t spsr_svc;
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u_register_t sp_svc;
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u_register_t lr_svc;
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u_register_t spsr_abt;
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u_register_t sp_abt;
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u_register_t lr_abt;
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u_register_t spsr_und;
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u_register_t sp_und;
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u_register_t lr_und;
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u_register_t spsr_mon;
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/* No need to save 'sp_mon' because we are already in monitor mode */
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u_register_t lr_mon;
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} smc_ctx_t;
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/*
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* Compile time assertions related to the 'smc_context' structure to
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* ensure that the assembler and the compiler view of the offsets of
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* the structure members is the same.
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*/
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CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), \
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assert_smc_ctx_greg_r0_offset_mismatch);
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CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), \
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assert_smc_ctx_greg_r1_offset_mismatch);
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CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), \
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assert_smc_ctx_greg_r2_offset_mismatch);
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CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \
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assert_smc_ctx_greg_r3_offset_mismatch);
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CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), \
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assert_smc_ctx_greg_r4_offset_mismatch);
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CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), \
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assert_smc_ctx_sp_usr_offset_mismatch);
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CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), \
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assert_smc_ctx_lr_mon_offset_mismatch);
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CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), \
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assert_smc_ctx_spsr_mon_offset_mismatch);
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CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch);
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/* Convenience macros to return from SMC handler */
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#define SMC_RET0(_h) { \
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return (uintptr_t)(_h); \
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}
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#define SMC_RET1(_h, _r0) { \
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((smc_ctx_t *)(_h))->r0 = (_r0); \
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SMC_RET0(_h); \
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}
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#define SMC_RET2(_h, _r0, _r1) { \
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((smc_ctx_t *)(_h))->r1 = (_r1); \
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SMC_RET1(_h, (_r0)); \
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}
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#define SMC_RET3(_h, _r0, _r1, _r2) { \
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((smc_ctx_t *)(_h))->r2 = (_r2); \
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SMC_RET2(_h, (_r0), (_r1)); \
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}
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#define SMC_RET4(_h, _r0, _r1, _r2, _r3) { \
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((smc_ctx_t *)(_h))->r3 = (_r3); \
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SMC_RET3(_h, (_r0), (_r1), (_r2)); \
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}
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/* Return a UUID in the SMC return registers */
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#define SMC_UUID_RET(_h, _uuid) \
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SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \
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((const uint32_t *) &(_uuid))[1], \
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((const uint32_t *) &(_uuid))[2], \
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((const uint32_t *) &(_uuid))[3])
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/*
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* Helper macro to retrieve the SMC parameters from smc_ctx_t.
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*/
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#define get_smc_params_from_ctx(_hdl, _r1, _r2, _r3, _r4) { \
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_r1 = ((smc_ctx_t *)_hdl)->r1; \
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_r2 = ((smc_ctx_t *)_hdl)->r2; \
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_r3 = ((smc_ctx_t *)_hdl)->r3; \
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_r4 = ((smc_ctx_t *)_hdl)->r4; \
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}
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/* ------------------------------------------------------------------------
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* Helper APIs for setting and retrieving appropriate `smc_ctx_t`.
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* These functions need to implemented by the BL including this library.
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* ------------------------------------------------------------------------
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*/
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/* Get the pointer to `smc_ctx_t` corresponding to the security state. */
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void *smc_get_ctx(int security_state);
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/* Set the next `smc_ctx_t` corresponding to the security state. */
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void smc_set_next_ctx(int security_state);
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/* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */
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void *smc_get_next_ctx(void);
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#endif /*__ASSEMBLY__*/
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#endif /* __SMCC_HELPERS_H__ */
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@ -0,0 +1,118 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SMCC_MACROS_S__
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#define __SMCC_MACROS_S__
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#include <arch.h>
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/*
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* Macro to save the General purpose registers including the banked
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* registers to the SMC context on entry due a SMC call. On return, r0
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* contains the pointer to the `smc_context_t`.
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*/
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.macro smcc_save_gp_mode_regs
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push {r0-r3, lr}
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ldcopr r0, SCR
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and r0, r0, #SCR_NS_BIT
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bl smc_get_ctx
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/* Save r4 - r12 in the SMC context */
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add r1, r0, #SMC_CTX_GPREG_R4
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stm r1!, {r4-r12}
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/*
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* Pop r0 - r3, lr to r4 - r7, lr from stack and then save
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* it to SMC context.
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*/
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pop {r4-r7, lr}
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stm r0, {r4-r7}
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/* Save the banked registers including the current SPSR and LR */
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mrs r4, sp_usr
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mrs r5, lr_usr
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mrs r6, spsr_irq
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mrs r7, sp_irq
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mrs r8, lr_irq
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mrs r9, spsr_fiq
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mrs r10, sp_fiq
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mrs r11, lr_fiq
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mrs r12, spsr_svc
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stm r1!, {r4-r12}
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mrs r4, sp_svc
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mrs r5, lr_svc
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mrs r6, spsr_abt
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mrs r7, sp_abt
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mrs r8, lr_abt
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mrs r9, spsr_und
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mrs r10, sp_und
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mrs r11, lr_und
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mrs r12, spsr
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stm r1!, {r4-r12, lr}
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.endm
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/*
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* Macro to restore the General purpose registers including the banked
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* registers from the SMC context prior to exit from the SMC call.
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* r0 must point to the `smc_context_t` to restore from.
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*/
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.macro smcc_restore_gp_mode_regs
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/* Restore the banked registers including the current SPSR and LR */
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add r1, r0, #SMC_CTX_SP_USR
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ldm r1!, {r4-r12}
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msr sp_usr, r4
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msr lr_usr, r5
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msr spsr_irq, r6
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msr sp_irq, r7
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msr lr_irq, r8
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msr spsr_fiq, r9
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msr sp_fiq, r10
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msr lr_fiq, r11
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msr spsr_svc, r12
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ldm r1!, {r4-r12, lr}
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msr sp_svc, r4
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msr lr_svc, r5
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msr spsr_abt, r6
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msr sp_abt, r7
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msr lr_abt, r8
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msr spsr_und, r9
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msr sp_und, r10
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msr lr_und, r11
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msr spsr, r12
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/* Restore the rest of the general purpose registers */
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ldm r0, {r0-r12}
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.endm
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#endif /* __SMCC_MACROS_S__ */
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