Update base code to not rely on undefined overflow behaviour

This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: Iddd6f38139a4c6e500468b4fc48d04e0939f574e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
This commit is contained in:
Justin Chadwell 2019-07-03 14:15:22 +01:00
parent d3b6df7c3b
commit 3e43121ed1
2 changed files with 3 additions and 3 deletions

View File

@ -82,7 +82,7 @@
#define UECDME 0x48
/* UTP Transfer Request Interrupt Aggregation Control Register */
#define UTRIACR 0x4C
#define UTRIACR_IAEN (1 << 31)
#define UTRIACR_IAEN (1U << 31)
#define UTRIACR_IAPWEN (1 << 24)
#define UTRIACR_IASB (1 << 20)
#define UTRIACR_CTR (1 << 16)

View File

@ -122,8 +122,8 @@ CASSERT(PLAT_PHY_ADDR_SPACE_SIZE == (1ULL << 32), invalid_paddr_space_size);
#define DACR_DOMAIN_PERM_CLIENT 0x1
#define DACR_DOMAIN_PERM_MANAGER 0x3
#define NUM_1MB_IN_4GB (1 << 12)
#define NUM_4K_IN_1MB (1 << 8)
#define NUM_1MB_IN_4GB (1U << 12)
#define NUM_4K_IN_1MB (1U << 8)
#define ONE_MB_SHIFT 20