From 3e881a8834a955f1e552300bdbf1dafd02ea8f1c Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Mon, 17 May 2021 11:25:37 +0200 Subject: [PATCH] fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards Set Ethernet source clock on PLL4P. This is required to enable PTP. Signed-off-by: Yann Gautier Change-Id: Ia64fbb681d3f04f2b90f373c5eb044f5daa2836c --- fdts/stm32mp157c-ed1.dts | 2 +- fdts/stm32mp15xx-dkx.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts index d47109678..47b2b1a81 100644 --- a/fdts/stm32mp157c-ed1.dts +++ b/fdts/stm32mp157c-ed1.dts @@ -232,7 +232,7 @@ CLK_CKPER_HSE CLK_FMC_ACLK CLK_QSPI_ACLK - CLK_ETH_DISABLED + CLK_ETH_PLL4P CLK_SDMMC12_PLL4P CLK_DSI_DSIPLL CLK_STGEN_HSE diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi index d6458a8a2..69b48285a 100644 --- a/fdts/stm32mp15xx-dkx.dtsi +++ b/fdts/stm32mp15xx-dkx.dtsi @@ -222,7 +222,7 @@ CLK_CKPER_HSE CLK_FMC_ACLK CLK_QSPI_ACLK - CLK_ETH_DISABLED + CLK_ETH_PLL4P CLK_SDMMC12_PLL4P CLK_DSI_DSIPLL CLK_STGEN_HSE