diff --git a/drivers/arm/gic/v3/gic600ae_fmu.c b/drivers/arm/gic/v3/gic600ae_fmu.c
index 2233bbf93..efca08fdd 100644
--- a/drivers/arm/gic/v3/gic600ae_fmu.c
+++ b/drivers/arm/gic/v3/gic600ae_fmu.c
@@ -268,8 +268,12 @@ void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask,
 	/* Enable error detection for all error records */
 	for (unsigned int i = 0U; i < num_blk; i++) {
 
-		/* Skip next steps if the block is not present */
+		/*
+		 * Disable all safety mechanisms for blocks that are not
+		 * present and skip the next steps.
+		 */
 		if ((blk_present_mask & BIT(i)) == 0U) {
+			gic_fmu_disable_all_sm_blkid(base, i);
 			continue;
 		}
 
diff --git a/drivers/arm/gic/v3/gic600ae_fmu_helpers.c b/drivers/arm/gic/v3/gic600ae_fmu_helpers.c
index 4aa0efb32..09806dcfc 100644
--- a/drivers/arm/gic/v3/gic600ae_fmu_helpers.c
+++ b/drivers/arm/gic/v3/gic600ae_fmu_helpers.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -258,3 +258,47 @@ void gic_fmu_write_pingmask(uintptr_t base, uint64_t val)
 {
 	GIC_FMU_WRITE_64(base, GICFMU_PINGMASK, 0, val);
 }
+
+/*
+ * Helper function to disable all safety mechanisms for a given block
+ */
+void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid)
+{
+	uint32_t smen, max_smid = U(0);
+
+	/* Sanity check block ID */
+	assert((blkid >= FMU_BLK_GICD) && (blkid <= FMU_BLK_PPI31));
+
+	/* Find the max safety mechanism ID for the block */
+	switch (blkid) {
+	case FMU_BLK_GICD:
+		max_smid = FMU_SMID_GICD_MAX;
+		break;
+
+	case FMU_BLK_SPICOL:
+		max_smid = FMU_SMID_SPICOL_MAX;
+		break;
+
+	case FMU_BLK_WAKERQ:
+		max_smid = FMU_SMID_WAKERQ_MAX;
+		break;
+
+	case FMU_BLK_ITS0...FMU_BLK_ITS7:
+		max_smid = FMU_SMID_ITS_MAX;
+		break;
+
+	case FMU_BLK_PPI0...FMU_BLK_PPI31:
+		max_smid = FMU_SMID_PPI_MAX;
+		break;
+
+	default:
+		assert(false);
+		break;
+	}
+
+	/* Disable all Safety Mechanisms for a given block id */
+	for (unsigned int i = 0U; i < max_smid; i++) {
+		smen = (blkid << FMU_SMEN_BLK_SHIFT) | (i << FMU_SMEN_SMID_SHIFT);
+		gic_fmu_write_smen(base, smen);
+	}
+}
diff --git a/include/drivers/arm/gic600ae_fmu.h b/include/drivers/arm/gic600ae_fmu.h
index f7dcbb8a2..904a5f984 100644
--- a/include/drivers/arm/gic600ae_fmu.h
+++ b/include/drivers/arm/gic600ae_fmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -86,10 +86,10 @@
 
 /* Safety Mechamism limit */
 #define FMU_SMID_GICD_MAX	U(33)
+#define FMU_SMID_PPI_MAX	U(12)
+#define FMU_SMID_ITS_MAX	U(14)
 #define FMU_SMID_SPICOL_MAX	U(5)
 #define FMU_SMID_WAKERQ_MAX	U(2)
-#define FMU_SMID_ITS_MAX	U(14)
-#define FMU_SMID_PPI_MAX	U(12)
 
 /* MBIST Safety Mechanism ID */
 #define GICD_MBIST_REQ_ERROR	U(23)
@@ -142,6 +142,7 @@ void gic_fmu_write_pingnow(uintptr_t base, uint32_t val);
 void gic_fmu_write_smen(uintptr_t base, uint32_t val);
 void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val);
 void gic_fmu_write_pingmask(uintptr_t base, uint64_t val);
+void gic_fmu_disable_all_sm_blkid(uintptr_t base, unsigned int blkid);
 
 void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask, bool errctlr_ce_en, bool errctlr_ue_en);
 void gic600_fmu_enable_ping(uint64_t base, uint64_t blk_present_mask,