gic: Fix types
Change-Id: I6a2adef87c20f9279446a54b7e69618fba3d2a25 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz
parent
8782922c25
commit
3fea9c8b8e
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@ -18,7 +18,8 @@
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*/
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unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> IGROUPR_SHIFT;
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unsigned int n = id >> IGROUPR_SHIFT;
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return mmio_read_32(base + GICD_IGROUPR + (n << 2));
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}
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@ -28,7 +29,8 @@ unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id)
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*/
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unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> ISENABLER_SHIFT;
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unsigned int n = id >> ISENABLER_SHIFT;
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return mmio_read_32(base + GICD_ISENABLER + (n << 2));
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}
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@ -38,7 +40,8 @@ unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
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*/
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unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> ICENABLER_SHIFT;
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unsigned int n = id >> ICENABLER_SHIFT;
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return mmio_read_32(base + GICD_ICENABLER + (n << 2));
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}
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@ -48,7 +51,8 @@ unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id)
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*/
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unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> ISPENDR_SHIFT;
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unsigned int n = id >> ISPENDR_SHIFT;
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return mmio_read_32(base + GICD_ISPENDR + (n << 2));
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}
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@ -58,7 +62,8 @@ unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id)
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*/
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unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> ICPENDR_SHIFT;
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unsigned int n = id >> ICPENDR_SHIFT;
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return mmio_read_32(base + GICD_ICPENDR + (n << 2));
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}
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@ -68,7 +73,8 @@ unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id)
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*/
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unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> ISACTIVER_SHIFT;
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unsigned int n = id >> ISACTIVER_SHIFT;
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return mmio_read_32(base + GICD_ISACTIVER + (n << 2));
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}
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@ -78,7 +84,8 @@ unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id)
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*/
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unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> ICACTIVER_SHIFT;
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unsigned int n = id >> ICACTIVER_SHIFT;
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return mmio_read_32(base + GICD_ICACTIVER + (n << 2));
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}
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@ -88,7 +95,8 @@ unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id)
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*/
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unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> IPRIORITYR_SHIFT;
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unsigned int n = id >> IPRIORITYR_SHIFT;
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return mmio_read_32(base + GICD_IPRIORITYR + (n << 2));
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}
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@ -98,7 +106,8 @@ unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id)
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*/
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unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> ICFGR_SHIFT;
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unsigned int n = id >> ICFGR_SHIFT;
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return mmio_read_32(base + GICD_ICFGR + (n << 2));
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}
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@ -108,7 +117,8 @@ unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id)
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*/
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unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id)
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{
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unsigned n = id >> NSACR_SHIFT;
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unsigned int n = id >> NSACR_SHIFT;
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return mmio_read_32(base + GICD_NSACR + (n << 2));
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}
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@ -121,7 +131,8 @@ unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id)
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*/
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void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> IGROUPR_SHIFT;
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unsigned int n = id >> IGROUPR_SHIFT;
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mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
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}
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@ -131,7 +142,8 @@ void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val)
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*/
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void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> ISENABLER_SHIFT;
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unsigned int n = id >> ISENABLER_SHIFT;
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mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
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}
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@ -141,7 +153,8 @@ void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val)
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*/
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void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> ICENABLER_SHIFT;
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unsigned int n = id >> ICENABLER_SHIFT;
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mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
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}
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@ -151,7 +164,8 @@ void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val)
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*/
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void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> ISPENDR_SHIFT;
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unsigned int n = id >> ISPENDR_SHIFT;
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mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
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}
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@ -161,7 +175,8 @@ void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val)
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*/
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void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> ICPENDR_SHIFT;
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unsigned int n = id >> ICPENDR_SHIFT;
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mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
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}
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@ -171,7 +186,8 @@ void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val)
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*/
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void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> ISACTIVER_SHIFT;
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unsigned int n = id >> ISACTIVER_SHIFT;
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mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
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}
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@ -181,7 +197,8 @@ void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val)
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*/
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void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> ICACTIVER_SHIFT;
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unsigned int n = id >> ICACTIVER_SHIFT;
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mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
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}
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@ -191,7 +208,8 @@ void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val)
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*/
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void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> IPRIORITYR_SHIFT;
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unsigned int n = id >> IPRIORITYR_SHIFT;
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mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
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}
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@ -201,7 +219,8 @@ void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
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*/
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void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> ICFGR_SHIFT;
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unsigned int n = id >> ICFGR_SHIFT;
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mmio_write_32(base + GICD_ICFGR + (n << 2), val);
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}
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@ -211,7 +230,8 @@ void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val)
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*/
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void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val)
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{
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unsigned n = id >> NSACR_SHIFT;
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unsigned int n = id >> NSACR_SHIFT;
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mmio_write_32(base + GICD_NSACR + (n << 2), val);
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}
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@ -223,87 +243,89 @@ void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val)
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******************************************************************************/
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unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
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unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
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unsigned int reg_val = gicd_read_igroupr(base, id);
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return (reg_val >> bit_num) & 0x1;
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return (reg_val >> bit_num) & 0x1U;
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}
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void gicd_set_igroupr(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
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unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
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unsigned int reg_val = gicd_read_igroupr(base, id);
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gicd_write_igroupr(base, id, reg_val | (1 << bit_num));
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gicd_write_igroupr(base, id, reg_val | (1U << bit_num));
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}
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void gicd_clr_igroupr(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
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unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
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unsigned int reg_val = gicd_read_igroupr(base, id);
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gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num));
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gicd_write_igroupr(base, id, reg_val & ~(1U << bit_num));
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}
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void gicd_set_isenabler(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
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unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
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gicd_write_isenabler(base, id, (1 << bit_num));
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gicd_write_isenabler(base, id, (1U << bit_num));
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}
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void gicd_set_icenabler(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
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unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
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gicd_write_icenabler(base, id, (1 << bit_num));
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gicd_write_icenabler(base, id, (1U << bit_num));
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}
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void gicd_set_ispendr(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
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unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
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gicd_write_ispendr(base, id, (1 << bit_num));
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gicd_write_ispendr(base, id, (1U << bit_num));
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}
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void gicd_set_icpendr(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
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unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
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gicd_write_icpendr(base, id, (1 << bit_num));
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gicd_write_icpendr(base, id, (1U << bit_num));
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}
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unsigned int gicd_get_isactiver(uintptr_t base, unsigned int id)
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{
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unsigned int bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
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unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
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unsigned int reg_val = gicd_read_isactiver(base, id);
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return (reg_val >> bit_num) & 0x1;
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return (reg_val >> bit_num) & 0x1U;
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}
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void gicd_set_isactiver(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
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unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
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gicd_write_isactiver(base, id, (1 << bit_num));
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gicd_write_isactiver(base, id, (1U << bit_num));
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}
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void gicd_set_icactiver(uintptr_t base, unsigned int id)
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{
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unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1);
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unsigned int bit_num = id & ((1U << ICACTIVER_SHIFT) - 1U);
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gicd_write_icactiver(base, id, (1 << bit_num));
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gicd_write_icactiver(base, id, (1U << bit_num));
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}
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void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
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{
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mmio_write_8(base + GICD_IPRIORITYR + id, pri & GIC_PRI_MASK);
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uint8_t val = pri & GIC_PRI_MASK;
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mmio_write_8(base + GICD_IPRIORITYR + id, val);
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}
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void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg)
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{
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/* Interrupt configuration is a 2-bit field */
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unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1);
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unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
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unsigned int bit_shift = bit_num << 1;
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uint32_t reg_val = gicd_read_icfgr(base, id);
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@ -94,24 +94,24 @@ void gicv2_spis_configure_defaults(uintptr_t gicd_base)
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num_ints = gicd_read_typer(gicd_base);
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num_ints &= TYPER_IT_LINES_NO_MASK;
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num_ints = (num_ints + 1) << 5;
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num_ints = (num_ints + 1U) << 5;
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/*
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* Treat all SPIs as G1NS by default. The number of interrupts is
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* calculated as 32 * (IT_LINES + 1). We do 32 at a time.
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*/
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for (index = MIN_SPI_ID; index < num_ints; index += 32)
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for (index = MIN_SPI_ID; index < num_ints; index += 32U)
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gicd_write_igroupr(gicd_base, index, ~0U);
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/* Setup the default SPI priorities doing four at a time */
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for (index = MIN_SPI_ID; index < num_ints; index += 4)
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for (index = MIN_SPI_ID; index < num_ints; index += 4U)
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gicd_write_ipriorityr(gicd_base,
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index,
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GICD_IPRIORITYR_DEF_VAL);
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/* Treat all SPIs as level triggered by default, 16 at a time */
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for (index = MIN_SPI_ID; index < num_ints; index += 16)
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gicd_write_icfgr(gicd_base, index, 0);
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for (index = MIN_SPI_ID; index < num_ints; index += 16U)
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gicd_write_icfgr(gicd_base, index, 0U);
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}
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#if !ERROR_DEPRECATED
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@ -125,7 +125,8 @@ void gicv2_secure_spis_configure(uintptr_t gicd_base,
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unsigned int index, irq_num;
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/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
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assert(num_ints ? (uintptr_t)sec_intr_list : 1);
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if (num_ints != 0U)
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assert(sec_intr_list != NULL);
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for (index = 0; index < num_ints; index++) {
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irq_num = sec_intr_list[index];
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@ -161,7 +162,8 @@ void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
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const interrupt_prop_t *prop_desc;
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/* Make sure there's a valid property array */
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assert(interrupt_props_num != 0 ? (uintptr_t) interrupt_props : 1);
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if (interrupt_props_num != 0U)
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assert(interrupt_props != NULL);
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for (i = 0; i < interrupt_props_num; i++) {
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prop_desc = &interrupt_props[i];
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@ -252,20 +254,21 @@ void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
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const interrupt_prop_t *prop_desc;
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/* Make sure there's a valid property array */
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assert(interrupt_props_num != 0 ? (uintptr_t) interrupt_props : 1);
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if (interrupt_props_num != 0U)
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assert(interrupt_props != NULL);
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/*
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* Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
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* more scalable approach as it avoids clearing the enable bits in the
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* GICD_CTLR.
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*/
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gicd_write_icenabler(gicd_base, 0, ~0);
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gicd_write_icenabler(gicd_base, 0U, ~0U);
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/* Setup the default PPI/SGI priorities doing four at a time */
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for (i = 0; i < MIN_SPI_ID; i += 4)
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for (i = 0U; i < MIN_SPI_ID; i += 4U)
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gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL);
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for (i = 0; i < interrupt_props_num; i++) {
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for (i = 0U; i < interrupt_props_num; i++) {
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prop_desc = &interrupt_props[i];
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if (prop_desc->intr_num >= MIN_SPI_ID)
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@ -12,6 +12,8 @@
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#include <gicv2.h>
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#include <interrupt_props.h>
|
||||
#include <spinlock.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "../common/gic_common_private.h"
|
||||
#include "gicv2_private.h"
|
||||
|
||||
|
|
@ -32,8 +34,8 @@ void gicv2_cpuif_enable(void)
|
|||
{
|
||||
unsigned int val;
|
||||
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicc_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicc_base != 0U);
|
||||
|
||||
/*
|
||||
* Enable the Group 0 interrupts, FIQEn and disable Group 0/1
|
||||
|
|
@ -55,8 +57,8 @@ void gicv2_cpuif_disable(void)
|
|||
{
|
||||
unsigned int val;
|
||||
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicc_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicc_base != 0U);
|
||||
|
||||
/* Disable secure, non-secure interrupts and disable their bypass */
|
||||
val = gicc_read_ctlr(driver_data->gicc_base);
|
||||
|
|
@ -74,8 +76,8 @@ void gicv2_pcpu_distif_init(void)
|
|||
{
|
||||
unsigned int ctlr;
|
||||
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
if (driver_data->interrupt_props != NULL) {
|
||||
|
|
@ -101,7 +103,7 @@ void gicv2_pcpu_distif_init(void)
|
|||
|
||||
/* Enable G0 interrupts if not already */
|
||||
ctlr = gicd_read_ctlr(driver_data->gicd_base);
|
||||
if ((ctlr & CTLR_ENABLE_G0_BIT) == 0) {
|
||||
if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) {
|
||||
gicd_write_ctlr(driver_data->gicd_base,
|
||||
ctlr | CTLR_ENABLE_G0_BIT);
|
||||
}
|
||||
|
|
@ -116,8 +118,8 @@ void gicv2_distif_init(void)
|
|||
{
|
||||
unsigned int ctlr;
|
||||
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
|
||||
/* Disable the distributor before going further */
|
||||
ctlr = gicd_read_ctlr(driver_data->gicd_base);
|
||||
|
|
@ -162,9 +164,10 @@ void gicv2_distif_init(void)
|
|||
void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
|
||||
{
|
||||
unsigned int gic_version;
|
||||
assert(plat_driver_data);
|
||||
assert(plat_driver_data->gicd_base);
|
||||
assert(plat_driver_data->gicc_base);
|
||||
|
||||
assert(plat_driver_data != NULL);
|
||||
assert(plat_driver_data->gicd_base != 0U);
|
||||
assert(plat_driver_data->gicc_base != 0U);
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
if (plat_driver_data->interrupt_props == NULL) {
|
||||
|
|
@ -212,7 +215,8 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
|
|||
* - interrupt priority drop.
|
||||
* - interrupt signal bypass.
|
||||
*/
|
||||
assert(gic_version == ARCH_REV_GICV2 || gic_version == ARCH_REV_GICV1);
|
||||
assert((gic_version == ARCH_REV_GICV2) ||
|
||||
(gic_version == ARCH_REV_GICV1));
|
||||
|
||||
driver_data = plat_driver_data;
|
||||
|
||||
|
|
@ -238,11 +242,11 @@ unsigned int gicv2_is_fiq_enabled(void)
|
|||
{
|
||||
unsigned int gicc_ctlr;
|
||||
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicc_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicc_base != 0U);
|
||||
|
||||
gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base);
|
||||
return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1;
|
||||
return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1U;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -255,8 +259,8 @@ unsigned int gicv2_is_fiq_enabled(void)
|
|||
******************************************************************************/
|
||||
unsigned int gicv2_get_pending_interrupt_type(void)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicc_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicc_base != 0U);
|
||||
|
||||
return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
|
||||
}
|
||||
|
|
@ -270,8 +274,8 @@ unsigned int gicv2_get_pending_interrupt_id(void)
|
|||
{
|
||||
unsigned int id;
|
||||
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicc_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicc_base != 0U);
|
||||
|
||||
id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK;
|
||||
|
||||
|
|
@ -292,8 +296,8 @@ unsigned int gicv2_get_pending_interrupt_id(void)
|
|||
******************************************************************************/
|
||||
unsigned int gicv2_acknowledge_interrupt(void)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicc_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicc_base != 0U);
|
||||
|
||||
return gicc_read_IAR(driver_data->gicc_base);
|
||||
}
|
||||
|
|
@ -304,8 +308,8 @@ unsigned int gicv2_acknowledge_interrupt(void)
|
|||
******************************************************************************/
|
||||
void gicv2_end_of_interrupt(unsigned int id)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicc_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicc_base != 0U);
|
||||
|
||||
gicc_write_EOIR(driver_data->gicc_base, id);
|
||||
}
|
||||
|
|
@ -318,8 +322,8 @@ void gicv2_end_of_interrupt(unsigned int id)
|
|||
******************************************************************************/
|
||||
unsigned int gicv2_get_interrupt_group(unsigned int id)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
|
||||
return gicd_get_igroupr(driver_data->gicd_base, id);
|
||||
}
|
||||
|
|
@ -330,8 +334,8 @@ unsigned int gicv2_get_interrupt_group(unsigned int id)
|
|||
******************************************************************************/
|
||||
unsigned int gicv2_get_running_priority(void)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicc_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicc_base != 0U);
|
||||
|
||||
return gicc_read_rpr(driver_data->gicc_base);
|
||||
}
|
||||
|
|
@ -344,21 +348,21 @@ unsigned int gicv2_get_running_priority(void)
|
|||
******************************************************************************/
|
||||
void gicv2_set_pe_target_mask(unsigned int proc_num)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data->target_masks);
|
||||
assert(proc_num < GICV2_MAX_TARGET_PE);
|
||||
assert(proc_num < driver_data->target_masks_num);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
assert(driver_data->target_masks != NULL);
|
||||
assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
|
||||
assert((unsigned int)proc_num < driver_data->target_masks_num);
|
||||
|
||||
/* Return if the target mask is already populated */
|
||||
if (driver_data->target_masks[proc_num])
|
||||
if (driver_data->target_masks[proc_num] != 0U)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Update target register corresponding to this CPU and flush for it to
|
||||
* be visible to other CPUs.
|
||||
*/
|
||||
if (driver_data->target_masks[proc_num] == 0) {
|
||||
if (driver_data->target_masks[proc_num] == 0U) {
|
||||
driver_data->target_masks[proc_num] =
|
||||
gicv2_get_cpuif_id(driver_data->gicd_base);
|
||||
#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
|
||||
|
|
@ -382,8 +386,8 @@ void gicv2_set_pe_target_mask(unsigned int proc_num)
|
|||
******************************************************************************/
|
||||
unsigned int gicv2_get_interrupt_active(unsigned int id)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
assert(id <= MAX_SPI_ID);
|
||||
|
||||
return gicd_get_isactiver(driver_data->gicd_base, id);
|
||||
|
|
@ -394,8 +398,8 @@ unsigned int gicv2_get_interrupt_active(unsigned int id)
|
|||
******************************************************************************/
|
||||
void gicv2_enable_interrupt(unsigned int id)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
assert(id <= MAX_SPI_ID);
|
||||
|
||||
/*
|
||||
|
|
@ -411,8 +415,8 @@ void gicv2_enable_interrupt(unsigned int id)
|
|||
******************************************************************************/
|
||||
void gicv2_disable_interrupt(unsigned int id)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
assert(id <= MAX_SPI_ID);
|
||||
|
||||
/*
|
||||
|
|
@ -429,8 +433,8 @@ void gicv2_disable_interrupt(unsigned int id)
|
|||
******************************************************************************/
|
||||
void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
assert(id <= MAX_SPI_ID);
|
||||
|
||||
gicd_set_ipriorityr(driver_data->gicd_base, id, priority);
|
||||
|
|
@ -442,8 +446,8 @@ void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority)
|
|||
******************************************************************************/
|
||||
void gicv2_set_interrupt_type(unsigned int id, unsigned int type)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
assert(id <= MAX_SPI_ID);
|
||||
|
||||
/* Serialize read-modify-write to Distributor registers */
|
||||
|
|
@ -456,7 +460,7 @@ void gicv2_set_interrupt_type(unsigned int id, unsigned int type)
|
|||
gicd_clr_igroupr(driver_data->gicd_base, id);
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
assert(false);
|
||||
break;
|
||||
}
|
||||
spin_unlock(&gic_lock);
|
||||
|
|
@ -472,20 +476,20 @@ void gicv2_raise_sgi(int sgi_num, int proc_num)
|
|||
{
|
||||
unsigned int sgir_val, target;
|
||||
|
||||
assert(driver_data);
|
||||
assert(proc_num < GICV2_MAX_TARGET_PE);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
|
||||
/*
|
||||
* Target masks array must have been supplied, and the core position
|
||||
* should be valid.
|
||||
*/
|
||||
assert(driver_data->target_masks);
|
||||
assert(proc_num < driver_data->target_masks_num);
|
||||
assert(driver_data->target_masks != NULL);
|
||||
assert((unsigned int)proc_num < driver_data->target_masks_num);
|
||||
|
||||
/* Don't raise SGI if the mask hasn't been populated */
|
||||
target = driver_data->target_masks[proc_num];
|
||||
assert(target != 0);
|
||||
assert(target != 0U);
|
||||
|
||||
sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, sgi_num);
|
||||
|
||||
|
|
@ -505,20 +509,20 @@ void gicv2_raise_sgi(int sgi_num, int proc_num)
|
|||
******************************************************************************/
|
||||
void gicv2_set_spi_routing(unsigned int id, int proc_num)
|
||||
{
|
||||
int target;
|
||||
unsigned int target;
|
||||
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
|
||||
assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID);
|
||||
assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID));
|
||||
|
||||
/*
|
||||
* Target masks array must have been supplied, and the core position
|
||||
* should be valid.
|
||||
*/
|
||||
assert(driver_data->target_masks);
|
||||
assert(proc_num < GICV2_MAX_TARGET_PE);
|
||||
assert(proc_num < driver_data->target_masks_num);
|
||||
assert(driver_data->target_masks != NULL);
|
||||
assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE);
|
||||
assert((unsigned int)proc_num < driver_data->target_masks_num);
|
||||
|
||||
if (proc_num < 0) {
|
||||
/* Target all PEs */
|
||||
|
|
@ -526,7 +530,7 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num)
|
|||
} else {
|
||||
/* Don't route interrupt if the mask hasn't been populated */
|
||||
target = driver_data->target_masks[proc_num];
|
||||
assert(target != 0);
|
||||
assert(target != 0U);
|
||||
}
|
||||
|
||||
gicd_set_itargetsr(driver_data->gicd_base, id, target);
|
||||
|
|
@ -537,8 +541,8 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num)
|
|||
******************************************************************************/
|
||||
void gicv2_clear_interrupt_pending(unsigned int id)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
|
||||
/* SGIs can't be cleared pending */
|
||||
assert(id >= MIN_PPI_ID);
|
||||
|
|
@ -556,8 +560,8 @@ void gicv2_clear_interrupt_pending(unsigned int id)
|
|||
******************************************************************************/
|
||||
void gicv2_set_interrupt_pending(unsigned int id)
|
||||
{
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicd_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
|
||||
/* SGIs can't be cleared pending */
|
||||
assert(id >= MIN_PPI_ID);
|
||||
|
|
@ -578,8 +582,8 @@ unsigned int gicv2_set_pmr(unsigned int mask)
|
|||
{
|
||||
unsigned int old_mask;
|
||||
|
||||
assert(driver_data);
|
||||
assert(driver_data->gicc_base);
|
||||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicc_base != 0U);
|
||||
|
||||
old_mask = gicc_read_pmr(driver_data->gicc_base);
|
||||
|
||||
|
|
|
|||
|
|
@ -50,7 +50,9 @@ static inline unsigned int gicd_get_itargetsr(uintptr_t base, unsigned int id)
|
|||
static inline void gicd_set_itargetsr(uintptr_t base, unsigned int id,
|
||||
unsigned int target)
|
||||
{
|
||||
mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK);
|
||||
uint8_t val = target & GIC_TARGET_CPU_MASK;
|
||||
|
||||
mmio_write_8(base + GICD_ITARGETSR + id, val);
|
||||
}
|
||||
|
||||
static inline void gicd_write_sgir(uintptr_t base, unsigned int val)
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@
|
|||
*/
|
||||
unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> IGRPMODR_SHIFT;
|
||||
unsigned int n = id >> IGRPMODR_SHIFT;
|
||||
|
||||
return mmio_read_32(base + GICD_IGRPMODR + (n << 2));
|
||||
}
|
||||
|
||||
|
|
@ -29,7 +30,8 @@ unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> IGRPMODR_SHIFT;
|
||||
unsigned int n = id >> IGRPMODR_SHIFT;
|
||||
|
||||
mmio_write_32(base + GICD_IGRPMODR + (n << 2), val);
|
||||
}
|
||||
|
||||
|
|
@ -39,10 +41,10 @@ void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val)
|
|||
*/
|
||||
unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
|
||||
unsigned int reg_val = gicd_read_igrpmodr(base, id);
|
||||
|
||||
return (reg_val >> bit_num) & 0x1;
|
||||
return (reg_val >> bit_num) & 0x1U;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -51,10 +53,10 @@ unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicd_set_igrpmodr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
|
||||
unsigned int reg_val = gicd_read_igrpmodr(base, id);
|
||||
|
||||
gicd_write_igrpmodr(base, id, reg_val | (1 << bit_num));
|
||||
gicd_write_igrpmodr(base, id, reg_val | (1U << bit_num));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -63,10 +65,10 @@ void gicd_set_igrpmodr(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicd_clr_igrpmodr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
|
||||
unsigned int reg_val = gicd_read_igrpmodr(base, id);
|
||||
|
||||
gicd_write_igrpmodr(base, id, reg_val & ~(1 << bit_num));
|
||||
gicd_write_igrpmodr(base, id, reg_val & ~(1U << bit_num));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -75,7 +77,8 @@ void gicd_clr_igrpmodr(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> IPRIORITYR_SHIFT;
|
||||
unsigned int n = id >> IPRIORITYR_SHIFT;
|
||||
|
||||
return mmio_read_32(base + GICR_IPRIORITYR + (n << 2));
|
||||
}
|
||||
|
||||
|
|
@ -85,7 +88,8 @@ unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> IPRIORITYR_SHIFT;
|
||||
unsigned int n = id >> IPRIORITYR_SHIFT;
|
||||
|
||||
mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val);
|
||||
}
|
||||
|
||||
|
|
@ -95,10 +99,10 @@ void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
|
|||
*/
|
||||
unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
|
||||
unsigned int reg_val = gicr_read_igroupr0(base);
|
||||
|
||||
return (reg_val >> bit_num) & 0x1;
|
||||
return (reg_val >> bit_num) & 0x1U;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -107,10 +111,10 @@ unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicr_set_igroupr0(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
|
||||
unsigned int reg_val = gicr_read_igroupr0(base);
|
||||
|
||||
gicr_write_igroupr0(base, reg_val | (1 << bit_num));
|
||||
gicr_write_igroupr0(base, reg_val | (1U << bit_num));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -119,10 +123,10 @@ void gicr_set_igroupr0(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicr_clr_igroupr0(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << IGROUPR_SHIFT) - 1U);
|
||||
unsigned int reg_val = gicr_read_igroupr0(base);
|
||||
|
||||
gicr_write_igroupr0(base, reg_val & ~(1 << bit_num));
|
||||
gicr_write_igroupr0(base, reg_val & ~(1U << bit_num));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -131,10 +135,10 @@ void gicr_clr_igroupr0(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
|
||||
unsigned int reg_val = gicr_read_igrpmodr0(base);
|
||||
|
||||
return (reg_val >> bit_num) & 0x1;
|
||||
return (reg_val >> bit_num) & 0x1U;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -143,10 +147,10 @@ unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicr_set_igrpmodr0(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
|
||||
unsigned int reg_val = gicr_read_igrpmodr0(base);
|
||||
|
||||
gicr_write_igrpmodr0(base, reg_val | (1 << bit_num));
|
||||
gicr_write_igrpmodr0(base, reg_val | (1U << bit_num));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -155,10 +159,10 @@ void gicr_set_igrpmodr0(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << IGRPMODR_SHIFT) - 1U);
|
||||
unsigned int reg_val = gicr_read_igrpmodr0(base);
|
||||
|
||||
gicr_write_igrpmodr0(base, reg_val & ~(1 << bit_num));
|
||||
gicr_write_igrpmodr0(base, reg_val & ~(1U << bit_num));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -167,9 +171,9 @@ void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicr_set_isenabler0(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << ISENABLER_SHIFT) - 1U);
|
||||
|
||||
gicr_write_isenabler0(base, (1 << bit_num));
|
||||
gicr_write_isenabler0(base, (1U << bit_num));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -178,9 +182,9 @@ void gicr_set_isenabler0(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicr_set_icenabler0(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << ICENABLER_SHIFT) - 1U);
|
||||
|
||||
gicr_write_icenabler0(base, (1 << bit_num));
|
||||
gicr_write_icenabler0(base, (1U << bit_num));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -189,10 +193,10 @@ void gicr_set_icenabler0(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << ISACTIVER_SHIFT) - 1U);
|
||||
unsigned int reg_val = gicr_read_isactiver0(base);
|
||||
|
||||
return (reg_val >> bit_num) & 0x1;
|
||||
return (reg_val >> bit_num) & 0x1U;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -201,9 +205,9 @@ unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicr_set_icpendr0(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << ICPENDR_SHIFT) - 1U);
|
||||
|
||||
gicr_write_icpendr0(base, (1 << bit_num));
|
||||
gicr_write_icpendr0(base, (1U << bit_num));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -212,9 +216,9 @@ void gicr_set_icpendr0(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicr_set_ispendr0(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
|
||||
unsigned int bit_num = id & ((1U << ISPENDR_SHIFT) - 1U);
|
||||
|
||||
gicr_write_ispendr0(base, (1 << bit_num));
|
||||
gicr_write_ispendr0(base, (1U << bit_num));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -223,7 +227,9 @@ void gicr_set_ispendr0(uintptr_t base, unsigned int id)
|
|||
*/
|
||||
void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
|
||||
{
|
||||
mmio_write_8(base + GICR_IPRIORITYR + id, pri & GIC_PRI_MASK);
|
||||
uint8_t val = pri & GIC_PRI_MASK;
|
||||
|
||||
mmio_write_8(base + GICR_IPRIORITYR + id, val);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -233,8 +239,8 @@ void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
|
|||
void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg)
|
||||
{
|
||||
/* Interrupt configuration is a 2-bit field */
|
||||
unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1);
|
||||
unsigned int bit_shift = bit_num << 1;
|
||||
unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
|
||||
unsigned int bit_shift = bit_num << 1U;
|
||||
|
||||
uint32_t reg_val = gicr_read_icfgr0(base);
|
||||
|
||||
|
|
@ -252,8 +258,8 @@ void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg)
|
|||
void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg)
|
||||
{
|
||||
/* Interrupt configuration is a 2-bit field */
|
||||
unsigned int bit_num = id & ((1 << ICFGR_SHIFT) - 1);
|
||||
unsigned int bit_shift = bit_num << 1;
|
||||
unsigned int bit_num = id & ((1U << ICFGR_SHIFT) - 1U);
|
||||
unsigned int bit_shift = bit_num << 1U;
|
||||
|
||||
uint32_t reg_val = gicr_read_icfgr1(base);
|
||||
|
||||
|
|
@ -274,13 +280,13 @@ void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base)
|
|||
* The WAKER_PS_BIT should be changed to 0
|
||||
* only when WAKER_CA_BIT is 1.
|
||||
*/
|
||||
assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT);
|
||||
assert((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U);
|
||||
|
||||
/* Mark the connected core as awake */
|
||||
gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT);
|
||||
|
||||
/* Wait till the WAKER_CA_BIT changes to 0 */
|
||||
while (gicr_read_waker(gicr_base) & WAKER_CA_BIT)
|
||||
while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) != 0U)
|
||||
;
|
||||
}
|
||||
|
||||
|
|
@ -295,7 +301,7 @@ void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base)
|
|||
gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT);
|
||||
|
||||
/* Wait till the WAKER_CA_BIT changes to 1 */
|
||||
while (!(gicr_read_waker(gicr_base) & WAKER_CA_BIT))
|
||||
while ((gicr_read_waker(gicr_base) & WAKER_CA_BIT) == 0U)
|
||||
;
|
||||
}
|
||||
|
||||
|
|
@ -312,10 +318,10 @@ void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
|
|||
{
|
||||
u_register_t mpidr;
|
||||
unsigned int proc_num;
|
||||
unsigned long long typer_val;
|
||||
uint64_t typer_val;
|
||||
uintptr_t rdistif_base = gicr_base;
|
||||
|
||||
assert(rdistif_base_addrs);
|
||||
assert(rdistif_base_addrs != NULL);
|
||||
|
||||
/*
|
||||
* Iterate over the Redistributor frames. Store the base address of each
|
||||
|
|
@ -326,7 +332,7 @@ void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
|
|||
*/
|
||||
do {
|
||||
typer_val = gicr_read_typer(rdistif_base);
|
||||
if (mpidr_to_core_pos) {
|
||||
if (mpidr_to_core_pos != NULL) {
|
||||
mpidr = mpidr_from_gicr_typer(typer_val);
|
||||
proc_num = mpidr_to_core_pos(mpidr);
|
||||
} else {
|
||||
|
|
@ -335,8 +341,8 @@ void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
|
|||
}
|
||||
assert(proc_num < rdistif_num);
|
||||
rdistif_base_addrs[proc_num] = rdistif_base;
|
||||
rdistif_base += (1 << GICR_PCPUBASE_SHIFT);
|
||||
} while (!(typer_val & TYPER_LAST_BIT));
|
||||
rdistif_base += (1U << GICR_PCPUBASE_SHIFT);
|
||||
} while ((typer_val & TYPER_LAST_BIT) == 0U);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -348,17 +354,17 @@ void gicv3_spis_config_defaults(uintptr_t gicd_base)
|
|||
|
||||
num_ints = gicd_read_typer(gicd_base);
|
||||
num_ints &= TYPER_IT_LINES_NO_MASK;
|
||||
num_ints = (num_ints + 1) << 5;
|
||||
num_ints = (num_ints + 1U) << 5;
|
||||
|
||||
/*
|
||||
* Treat all SPIs as G1NS by default. The number of interrupts is
|
||||
* calculated as 32 * (IT_LINES + 1). We do 32 at a time.
|
||||
*/
|
||||
for (index = MIN_SPI_ID; index < num_ints; index += 32)
|
||||
for (index = MIN_SPI_ID; index < num_ints; index += 32U)
|
||||
gicd_write_igroupr(gicd_base, index, ~0U);
|
||||
|
||||
/* Setup the default SPI priorities doing four at a time */
|
||||
for (index = MIN_SPI_ID; index < num_ints; index += 4)
|
||||
for (index = MIN_SPI_ID; index < num_ints; index += 4U)
|
||||
gicd_write_ipriorityr(gicd_base,
|
||||
index,
|
||||
GICD_IPRIORITYR_DEF_VAL);
|
||||
|
|
@ -367,8 +373,8 @@ void gicv3_spis_config_defaults(uintptr_t gicd_base)
|
|||
* Treat all SPIs as level triggered by default, write 16 at
|
||||
* a time
|
||||
*/
|
||||
for (index = MIN_SPI_ID; index < num_ints; index += 16)
|
||||
gicd_write_icfgr(gicd_base, index, 0);
|
||||
for (index = MIN_SPI_ID; index < num_ints; index += 16U)
|
||||
gicd_write_icfgr(gicd_base, index, 0U);
|
||||
}
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
|
|
@ -385,9 +391,10 @@ void gicv3_secure_spis_config(uintptr_t gicd_base,
|
|||
|
||||
assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
|
||||
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
|
||||
assert(num_ints ? (uintptr_t)sec_intr_list : 1);
|
||||
if (num_ints != 0U)
|
||||
assert(sec_intr_list != NULL);
|
||||
|
||||
for (index = 0; index < num_ints; index++) {
|
||||
for (index = 0U; index < num_ints; index++) {
|
||||
irq_num = sec_intr_list[index];
|
||||
if (irq_num >= MIN_SPI_ID) {
|
||||
|
||||
|
|
@ -407,7 +414,7 @@ void gicv3_secure_spis_config(uintptr_t gicd_base,
|
|||
|
||||
/* Target SPIs to the primary CPU */
|
||||
gic_affinity_val =
|
||||
gicd_irouter_val_from_mpidr(read_mpidr(), 0);
|
||||
gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
|
||||
gicd_write_irouter(gicd_base,
|
||||
irq_num,
|
||||
gic_affinity_val);
|
||||
|
|
@ -430,12 +437,13 @@ unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
|
|||
unsigned int i;
|
||||
const interrupt_prop_t *current_prop;
|
||||
unsigned long long gic_affinity_val;
|
||||
unsigned int ctlr_enable = 0;
|
||||
unsigned int ctlr_enable = 0U;
|
||||
|
||||
/* Make sure there's a valid property array */
|
||||
assert(interrupt_props_num > 0 ? interrupt_props != NULL : 1);
|
||||
if (interrupt_props_num > 0U)
|
||||
assert(interrupt_props != NULL);
|
||||
|
||||
for (i = 0; i < interrupt_props_num; i++) {
|
||||
for (i = 0U; i < interrupt_props_num; i++) {
|
||||
current_prop = &interrupt_props[i];
|
||||
|
||||
if (current_prop->intr_num < MIN_SPI_ID)
|
||||
|
|
@ -464,7 +472,8 @@ unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
|
|||
current_prop->intr_pri);
|
||||
|
||||
/* Target SPIs to the primary CPU */
|
||||
gic_affinity_val = gicd_irouter_val_from_mpidr(read_mpidr(), 0);
|
||||
gic_affinity_val =
|
||||
gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
|
||||
gicd_write_irouter(gicd_base, current_prop->intr_num,
|
||||
gic_affinity_val);
|
||||
|
||||
|
|
@ -487,20 +496,20 @@ void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)
|
|||
* more scalable approach as it avoids clearing the enable bits in the
|
||||
* GICD_CTLR
|
||||
*/
|
||||
gicr_write_icenabler0(gicr_base, ~0);
|
||||
gicr_write_icenabler0(gicr_base, ~0U);
|
||||
gicr_wait_for_pending_write(gicr_base);
|
||||
|
||||
/* Treat all SGIs/PPIs as G1NS by default. */
|
||||
gicr_write_igroupr0(gicr_base, ~0U);
|
||||
|
||||
/* Setup the default PPI/SGI priorities doing four at a time */
|
||||
for (index = 0; index < MIN_SPI_ID; index += 4)
|
||||
for (index = 0U; index < MIN_SPI_ID; index += 4U)
|
||||
gicr_write_ipriorityr(gicr_base,
|
||||
index,
|
||||
GICD_IPRIORITYR_DEF_VAL);
|
||||
|
||||
/* Configure all PPIs as level triggered by default */
|
||||
gicr_write_icfgr1(gicr_base, 0);
|
||||
gicr_write_icfgr1(gicr_base, 0U);
|
||||
}
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
|
|
@ -516,7 +525,8 @@ void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
|
|||
|
||||
assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
|
||||
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
|
||||
assert(num_ints ? (uintptr_t)sec_intr_list : 1);
|
||||
if (num_ints != 0U)
|
||||
assert(sec_intr_list != NULL);
|
||||
|
||||
for (index = 0; index < num_ints; index++) {
|
||||
irq_num = sec_intr_list[index];
|
||||
|
|
@ -552,12 +562,13 @@ unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
|
|||
{
|
||||
unsigned int i;
|
||||
const interrupt_prop_t *current_prop;
|
||||
unsigned int ctlr_enable = 0;
|
||||
unsigned int ctlr_enable = 0U;
|
||||
|
||||
/* Make sure there's a valid property array */
|
||||
assert(interrupt_props_num > 0 ? interrupt_props != NULL : 1);
|
||||
if (interrupt_props_num > 0U)
|
||||
assert(interrupt_props != NULL);
|
||||
|
||||
for (i = 0; i < interrupt_props_num; i++) {
|
||||
for (i = 0U; i < interrupt_props_num; i++) {
|
||||
current_prop = &interrupt_props[i];
|
||||
|
||||
if (current_prop->intr_num >= MIN_SPI_ID)
|
||||
|
|
|
|||
|
|
@ -34,21 +34,21 @@ static spinlock_t gic_lock;
|
|||
/* Helper macros to save and restore GICD registers to and from the context */
|
||||
#define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \
|
||||
do { \
|
||||
for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \
|
||||
int_id += (1 << REG##_SHIFT)) { \
|
||||
for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
|
||||
int_id += (1U << REG##_SHIFT)) { \
|
||||
gicd_write_##reg(base, int_id, \
|
||||
ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \
|
||||
} \
|
||||
} while (0)
|
||||
} while (false)
|
||||
|
||||
#define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \
|
||||
do { \
|
||||
for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \
|
||||
int_id += (1 << REG##_SHIFT)) { \
|
||||
for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
|
||||
int_id += (1U << REG##_SHIFT)) { \
|
||||
ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\
|
||||
gicd_read_##reg(base, int_id); \
|
||||
} \
|
||||
} while (0)
|
||||
} while (false)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -59,11 +59,11 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
|
|||
{
|
||||
unsigned int gic_version;
|
||||
|
||||
assert(plat_driver_data);
|
||||
assert(plat_driver_data->gicd_base);
|
||||
assert(plat_driver_data->gicr_base);
|
||||
assert(plat_driver_data->rdistif_num);
|
||||
assert(plat_driver_data->rdistif_base_addrs);
|
||||
assert(plat_driver_data != NULL);
|
||||
assert(plat_driver_data->gicd_base != 0U);
|
||||
assert(plat_driver_data->gicr_base != 0U);
|
||||
assert(plat_driver_data->rdistif_num != 0U);
|
||||
assert(plat_driver_data->rdistif_base_addrs != NULL);
|
||||
|
||||
assert(IS_IN_EL3());
|
||||
|
||||
|
|
@ -109,10 +109,10 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
|
|||
|
||||
/* Check for system register support */
|
||||
#ifdef AARCH32
|
||||
assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT));
|
||||
assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
|
||||
#else
|
||||
assert(read_id_aa64pfr0_el1() &
|
||||
(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT));
|
||||
assert((read_id_aa64pfr0_el1() &
|
||||
(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
|
||||
#endif /* AARCH32 */
|
||||
|
||||
/* The GIC version should be 3.0 */
|
||||
|
|
@ -170,8 +170,8 @@ void gicv3_distif_init(void)
|
|||
{
|
||||
unsigned int bitmap = 0;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
|
||||
assert(IS_IN_EL3());
|
||||
|
||||
|
|
@ -245,16 +245,16 @@ void gicv3_distif_init(void)
|
|||
void gicv3_rdistif_init(unsigned int proc_num)
|
||||
{
|
||||
uintptr_t gicr_base;
|
||||
unsigned int bitmap = 0;
|
||||
unsigned int bitmap = 0U;
|
||||
uint32_t ctlr;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
|
||||
ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base);
|
||||
assert(ctlr & CTLR_ARE_S_BIT);
|
||||
assert((ctlr & CTLR_ARE_S_BIT) != 0U);
|
||||
|
||||
assert(IS_IN_EL3());
|
||||
|
||||
|
|
@ -333,9 +333,9 @@ void gicv3_cpuif_enable(unsigned int proc_num)
|
|||
unsigned int scr_el3;
|
||||
unsigned int icc_sre_el3;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
assert(IS_IN_EL3());
|
||||
|
||||
/* Mark the connected core as awake */
|
||||
|
|
@ -353,7 +353,7 @@ void gicv3_cpuif_enable(unsigned int proc_num)
|
|||
icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
|
||||
write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
|
||||
|
||||
scr_el3 = read_scr_el3();
|
||||
scr_el3 = (uint32_t) read_scr_el3();
|
||||
|
||||
/*
|
||||
* Switch to NS state to write Non secure ICC_SRE_EL1 and
|
||||
|
|
@ -393,9 +393,9 @@ void gicv3_cpuif_disable(unsigned int proc_num)
|
|||
{
|
||||
uintptr_t gicr_base;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
|
||||
assert(IS_IN_EL3());
|
||||
|
||||
|
|
@ -429,14 +429,14 @@ unsigned int gicv3_get_pending_interrupt_id(void)
|
|||
unsigned int id;
|
||||
|
||||
assert(IS_IN_EL3());
|
||||
id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
|
||||
id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
|
||||
|
||||
/*
|
||||
* If the ID is special identifier corresponding to G1S or G1NS
|
||||
* interrupt, then read the highest pending group 1 interrupt.
|
||||
*/
|
||||
if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID))
|
||||
return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
|
||||
return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
|
||||
|
||||
return id;
|
||||
}
|
||||
|
|
@ -453,7 +453,7 @@ unsigned int gicv3_get_pending_interrupt_id(void)
|
|||
unsigned int gicv3_get_pending_interrupt_type(void)
|
||||
{
|
||||
assert(IS_IN_EL3());
|
||||
return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
|
||||
return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -473,10 +473,10 @@ unsigned int gicv3_get_interrupt_type(unsigned int id,
|
|||
uintptr_t gicr_base;
|
||||
|
||||
assert(IS_IN_EL3());
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
|
||||
/* Ensure the parameters are valid */
|
||||
assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID);
|
||||
assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID));
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
|
||||
/* All LPI interrupts are Group 1 non secure */
|
||||
|
|
@ -484,12 +484,12 @@ unsigned int gicv3_get_interrupt_type(unsigned int id,
|
|||
return INTR_GROUP1NS;
|
||||
|
||||
if (id < MIN_SPI_ID) {
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != 0U);
|
||||
gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
|
||||
igroup = gicr_get_igroupr0(gicr_base, id);
|
||||
grpmodr = gicr_get_igrpmodr0(gicr_base, id);
|
||||
} else {
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id);
|
||||
grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id);
|
||||
}
|
||||
|
|
@ -498,11 +498,11 @@ unsigned int gicv3_get_interrupt_type(unsigned int id,
|
|||
* If the IGROUP bit is set, then it is a Group 1 Non secure
|
||||
* interrupt
|
||||
*/
|
||||
if (igroup)
|
||||
if (igroup != 0U)
|
||||
return INTR_GROUP1NS;
|
||||
|
||||
/* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
|
||||
if (grpmodr)
|
||||
if (grpmodr != 0U)
|
||||
return INTR_GROUP1S;
|
||||
|
||||
/* Else it is a Group 0 Secure interrupt */
|
||||
|
|
@ -522,12 +522,12 @@ unsigned int gicv3_get_interrupt_type(unsigned int id,
|
|||
*****************************************************************************/
|
||||
void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx)
|
||||
{
|
||||
int i;
|
||||
unsigned int i;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(IS_IN_EL3());
|
||||
assert(its_ctx);
|
||||
assert(gits_base);
|
||||
assert(its_ctx != NULL);
|
||||
assert(gits_base != 0U);
|
||||
|
||||
its_ctx->gits_ctlr = gits_read_ctlr(gits_base);
|
||||
|
||||
|
|
@ -555,16 +555,16 @@ void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx
|
|||
*****************************************************************************/
|
||||
void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx)
|
||||
{
|
||||
int i;
|
||||
unsigned int i;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(IS_IN_EL3());
|
||||
assert(its_ctx);
|
||||
assert(gits_base);
|
||||
assert(its_ctx != NULL);
|
||||
assert(gits_base != 0U);
|
||||
|
||||
/* Assert that the GITS is disabled and quiescent */
|
||||
assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0);
|
||||
assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0);
|
||||
assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
|
||||
assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U);
|
||||
|
||||
gits_write_cbaser(gits_base, its_ctx->gits_cbaser);
|
||||
gits_write_cwriter(gits_base, its_ctx->gits_cwriter);
|
||||
|
|
@ -586,11 +586,11 @@ void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_
|
|||
uintptr_t gicr_base;
|
||||
unsigned int int_id;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
assert(IS_IN_EL3());
|
||||
assert(rdist_ctx);
|
||||
assert(rdist_ctx != NULL);
|
||||
|
||||
gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
|
||||
|
||||
|
|
@ -614,7 +614,7 @@ void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_
|
|||
rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base);
|
||||
rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base);
|
||||
for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
|
||||
int_id += (1 << IPRIORITYR_SHIFT)) {
|
||||
int_id += (1U << IPRIORITYR_SHIFT)) {
|
||||
rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] =
|
||||
gicr_read_ipriorityr(gicr_base, int_id);
|
||||
}
|
||||
|
|
@ -641,11 +641,11 @@ void gicv3_rdistif_init_restore(unsigned int proc_num,
|
|||
uintptr_t gicr_base;
|
||||
unsigned int int_id;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
assert(IS_IN_EL3());
|
||||
assert(rdist_ctx);
|
||||
assert(rdist_ctx != NULL);
|
||||
|
||||
gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
|
||||
|
||||
|
|
@ -664,7 +664,7 @@ void gicv3_rdistif_init_restore(unsigned int proc_num,
|
|||
* more scalable approach as it avoids clearing the enable bits in the
|
||||
* GICD_CTLR
|
||||
*/
|
||||
gicr_write_icenabler0(gicr_base, ~0);
|
||||
gicr_write_icenabler0(gicr_base, ~0U);
|
||||
/* Wait for pending writes to GICR_ICENABLER */
|
||||
gicr_wait_for_pending_write(gicr_base);
|
||||
|
||||
|
|
@ -682,7 +682,7 @@ void gicv3_rdistif_init_restore(unsigned int proc_num,
|
|||
gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0);
|
||||
|
||||
for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
|
||||
int_id += (1 << IPRIORITYR_SHIFT)) {
|
||||
int_id += (1U << IPRIORITYR_SHIFT)) {
|
||||
gicr_write_ipriorityr(gicr_base, int_id,
|
||||
rdist_ctx->gicr_ipriorityr[
|
||||
(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]);
|
||||
|
|
@ -722,18 +722,18 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
|
|||
{
|
||||
unsigned int num_ints;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
assert(IS_IN_EL3());
|
||||
assert(dist_ctx);
|
||||
assert(dist_ctx != NULL);
|
||||
|
||||
uintptr_t gicd_base = gicv3_driver_data->gicd_base;
|
||||
|
||||
num_ints = gicd_read_typer(gicd_base);
|
||||
num_ints &= TYPER_IT_LINES_NO_MASK;
|
||||
num_ints = (num_ints + 1) << 5;
|
||||
num_ints = (num_ints + 1U) << 5;
|
||||
|
||||
assert(num_ints <= MAX_SPI_ID + 1);
|
||||
assert(num_ints <= (MAX_SPI_ID + 1U));
|
||||
|
||||
/* Wait for pending write to complete */
|
||||
gicd_wait_for_pending_write(gicd_base);
|
||||
|
|
@ -784,12 +784,12 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
|
|||
*****************************************************************************/
|
||||
void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
|
||||
{
|
||||
unsigned int num_ints = 0;
|
||||
unsigned int num_ints = 0U;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
assert(IS_IN_EL3());
|
||||
assert(dist_ctx);
|
||||
assert(dist_ctx != NULL);
|
||||
|
||||
uintptr_t gicd_base = gicv3_driver_data->gicd_base;
|
||||
|
||||
|
|
@ -809,9 +809,9 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
|
|||
|
||||
num_ints = gicd_read_typer(gicd_base);
|
||||
num_ints &= TYPER_IT_LINES_NO_MASK;
|
||||
num_ints = (num_ints + 1) << 5;
|
||||
num_ints = (num_ints + 1U) << 5;
|
||||
|
||||
assert(num_ints <= MAX_SPI_ID + 1);
|
||||
assert(num_ints <= (MAX_SPI_ID + 1U));
|
||||
|
||||
/* Restore GICD_IGROUPR for INTIDs 32 - 1020 */
|
||||
RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
|
||||
|
|
@ -857,7 +857,7 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
|
|||
******************************************************************************/
|
||||
unsigned int gicv3_get_running_priority(void)
|
||||
{
|
||||
return read_icc_rpr_el1();
|
||||
return (unsigned int)read_icc_rpr_el1();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
@ -870,10 +870,10 @@ unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num)
|
|||
{
|
||||
unsigned int value;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
assert(id <= MAX_SPI_ID);
|
||||
|
||||
if (id < MIN_SPI_ID) {
|
||||
|
|
@ -894,10 +894,10 @@ unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num)
|
|||
******************************************************************************/
|
||||
void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num)
|
||||
{
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
assert(id <= MAX_SPI_ID);
|
||||
|
||||
/*
|
||||
|
|
@ -922,10 +922,10 @@ void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num)
|
|||
******************************************************************************/
|
||||
void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num)
|
||||
{
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
assert(id <= MAX_SPI_ID);
|
||||
|
||||
/*
|
||||
|
|
@ -960,10 +960,10 @@ void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
|
|||
{
|
||||
uintptr_t gicr_base;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
assert(id <= MAX_SPI_ID);
|
||||
|
||||
if (id < MIN_SPI_ID) {
|
||||
|
|
@ -982,29 +982,29 @@ void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
|
|||
void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
|
||||
unsigned int type)
|
||||
{
|
||||
unsigned int igroup = 0, grpmod = 0;
|
||||
bool igroup = false, grpmod = false;
|
||||
uintptr_t gicr_base;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
|
||||
switch (type) {
|
||||
case INTR_GROUP1S:
|
||||
igroup = 0;
|
||||
grpmod = 1;
|
||||
igroup = false;
|
||||
grpmod = true;
|
||||
break;
|
||||
case INTR_GROUP0:
|
||||
igroup = 0;
|
||||
grpmod = 0;
|
||||
igroup = false;
|
||||
grpmod = false;
|
||||
break;
|
||||
case INTR_GROUP1NS:
|
||||
igroup = 1;
|
||||
grpmod = 0;
|
||||
igroup = true;
|
||||
grpmod = false;
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
assert(false);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1040,7 +1040,7 @@ void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
|
|||
*
|
||||
* The target parameter must be a valid MPIDR in the system.
|
||||
******************************************************************************/
|
||||
void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target)
|
||||
void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target)
|
||||
{
|
||||
unsigned int tgt, aff3, aff2, aff1, aff0;
|
||||
uint64_t sgi_val;
|
||||
|
|
@ -1059,7 +1059,7 @@ void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target)
|
|||
* this PE.
|
||||
*/
|
||||
assert(aff0 < GICV3_MAX_SGI_TARGETS);
|
||||
tgt = BIT(aff0);
|
||||
tgt = BIT_32(aff0);
|
||||
|
||||
/* Raise SGI to PE specified by its affinity */
|
||||
sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF,
|
||||
|
|
@ -1090,11 +1090,11 @@ void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr
|
|||
unsigned long long aff;
|
||||
uint64_t router;
|
||||
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
|
||||
assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE));
|
||||
assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID);
|
||||
assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID));
|
||||
|
||||
aff = gicd_irouter_val_from_mpidr(mpidr, irm);
|
||||
gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff);
|
||||
|
|
@ -1105,7 +1105,7 @@ void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr
|
|||
*/
|
||||
if (irm == GICV3_IRM_ANY) {
|
||||
router = gicd_read_irouter(gicv3_driver_data->gicd_base, id);
|
||||
if (!((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK)) {
|
||||
if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) {
|
||||
ERROR("GICv3 implementation doesn't support routing ANY\n");
|
||||
panic();
|
||||
}
|
||||
|
|
@ -1119,10 +1119,10 @@ void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr
|
|||
******************************************************************************/
|
||||
void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num)
|
||||
{
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
|
||||
/*
|
||||
* Clear pending interrupt, and ensure that any shared variable updates
|
||||
|
|
@ -1145,10 +1145,10 @@ void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num)
|
|||
******************************************************************************/
|
||||
void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num)
|
||||
{
|
||||
assert(gicv3_driver_data);
|
||||
assert(gicv3_driver_data->gicd_base);
|
||||
assert(gicv3_driver_data != NULL);
|
||||
assert(gicv3_driver_data->gicd_base != 0U);
|
||||
assert(proc_num < gicv3_driver_data->rdistif_num);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs);
|
||||
assert(gicv3_driver_data->rdistif_base_addrs != NULL);
|
||||
|
||||
/*
|
||||
* Ensure that any shared variable updates depending on out of band
|
||||
|
|
@ -1172,7 +1172,7 @@ unsigned int gicv3_set_pmr(unsigned int mask)
|
|||
{
|
||||
unsigned int old_mask;
|
||||
|
||||
old_mask = read_icc_pmr_el1();
|
||||
old_mask = (uint32_t) read_icc_pmr_el1();
|
||||
|
||||
/*
|
||||
* Order memory updates w.r.t. PMR write, and ensure they're visible
|
||||
|
|
|
|||
|
|
@ -129,7 +129,7 @@ void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
|
|||
*/
|
||||
static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
|
||||
{
|
||||
while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT)
|
||||
while ((gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) != 0U)
|
||||
;
|
||||
}
|
||||
|
||||
|
|
@ -157,7 +157,7 @@ static inline void gicd_clr_ctlr(uintptr_t base,
|
|||
unsigned int rwp)
|
||||
{
|
||||
gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap);
|
||||
if (rwp)
|
||||
if (rwp != 0U)
|
||||
gicd_wait_for_pending_write(base);
|
||||
}
|
||||
|
||||
|
|
@ -166,7 +166,7 @@ static inline void gicd_set_ctlr(uintptr_t base,
|
|||
unsigned int rwp)
|
||||
{
|
||||
gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap);
|
||||
if (rwp)
|
||||
if (rwp != 0U)
|
||||
gicd_wait_for_pending_write(base);
|
||||
}
|
||||
|
||||
|
|
@ -207,13 +207,13 @@ static inline void gicr_write_waker(uintptr_t base, unsigned int val)
|
|||
*/
|
||||
static inline void gicr_wait_for_pending_write(uintptr_t gicr_base)
|
||||
{
|
||||
while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT)
|
||||
while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) != 0U)
|
||||
;
|
||||
}
|
||||
|
||||
static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base)
|
||||
{
|
||||
while (gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT)
|
||||
while ((gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) != 0U)
|
||||
;
|
||||
}
|
||||
|
||||
|
|
@ -376,14 +376,14 @@ static inline void gits_write_cwriter(uintptr_t base, uint64_t val)
|
|||
|
||||
static inline uint64_t gits_read_baser(uintptr_t base, unsigned int its_table_id)
|
||||
{
|
||||
assert(its_table_id < 8);
|
||||
return mmio_read_64(base + GITS_BASER + (8 * its_table_id));
|
||||
assert(its_table_id < 8U);
|
||||
return mmio_read_64(base + GITS_BASER + (8U * its_table_id));
|
||||
}
|
||||
|
||||
static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, uint64_t val)
|
||||
{
|
||||
assert(its_table_id < 8);
|
||||
mmio_write_64(base + GITS_BASER + (8 * its_table_id), val);
|
||||
assert(its_table_id < 8U);
|
||||
mmio_write_64(base + GITS_BASER + (8U * its_table_id), val);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -391,8 +391,8 @@ static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, u
|
|||
*/
|
||||
static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base)
|
||||
{
|
||||
assert(!(gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT));
|
||||
while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0)
|
||||
assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
|
||||
while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0U)
|
||||
;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -420,7 +420,7 @@ void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
|
|||
unsigned int priority);
|
||||
void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
|
||||
unsigned int type);
|
||||
void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target);
|
||||
void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target);
|
||||
void gicv3_set_spi_routing(unsigned int id, unsigned int irm,
|
||||
u_register_t mpidr);
|
||||
void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num);
|
||||
|
|
|
|||
Loading…
Reference in New Issue