andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

rcar_get3: drivers: ddr: Clean up common code 

Do minor coding style changes to the common DDR init code to make it
checkpatch compliant and move macros out into rcar_def.h.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I67eadf8099e4ff8702105c9e07b13f308d9dbe3d
This commit is contained in:
Marek Vasut 2019-08-07 18:05:05 +02:00
parent 3441952f61
commit 40c711a360
4 changed files with 61 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/staging/renesas/rcar/ddr/boot_init_dram.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,10 +9,10 @@
extern int32_t rcar_dram_init(void);
#define INITDRAM_OK (0)
#define INITDRAM_NG (0xffffffff)
#define INITDRAM_ERR_I (0xffffffff)
#define INITDRAM_ERR_O (0xfffffffe)
#define INITDRAM_ERR_T (0xfffffff0)
#define INITDRAM_OK 0
#define INITDRAM_NG 0xffffffff
#define INITDRAM_ERR_I 0xffffffff
#define INITDRAM_ERR_O 0xfffffffe
#define INITDRAM_ERR_T 0xfffffff0
#endif /* BOOT_INIT_DRAM_H */

93
drivers/staging/renesas/rcar/ddr/dram_sub_func.c
View File

@ -12,38 +12,30 @@
#if RCAR_SYSTEM_SUSPEND
/* Local defines */
#define DRAM_BACKUP_GPIO_USE (0)
#define DRAM_BACKUP_GPIO_USE 0
#include "iic_dvfs.h"
#if PMIC_ROHM_BD9571
#define PMIC_SLAVE_ADDR (0x30U)
#define PMIC_BKUP_MODE_CNT (0x20U)
#define PMIC_QLLM_CNT (0x27U)
#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U))
#define BIT_QLLM_DDR0_EN ((uint8_t)(1U << 0U))
#define BIT_QLLM_DDR1_EN ((uint8_t)(1U << 1U))
#define PMIC_SLAVE_ADDR 0x30U
#define PMIC_BKUP_MODE_CNT 0x20U
#define PMIC_QLLM_CNT 0x27U
#define BIT_BKUP_CTRL_OUT BIT(4)
#define BIT_QLLM_DDR0_EN BIT(0)
#define BIT_QLLM_DDR1_EN BIT(1)
#endif
#define GPIO_OUTDT1 (0xE6051008U)
#define GPIO_OUTDT3 (0xE6053008U)
#define GPIO_INDT3 (0xE605300CU)
#define GPIO_OUTDT6 (0xE6055408U)
#define GPIO_BKUP_REQB_SHIFT_SALVATOR 9U /* GP1_9 (BKUP_REQB) */
#define GPIO_BKUP_TRG_SHIFT_SALVATOR 8U /* GP1_8 (BKUP_TRG) */
#define GPIO_BKUP_REQB_SHIFT_EBISU 14U /* GP6_14(BKUP_REQB) */
#define GPIO_BKUP_TRG_SHIFT_EBISU 13U /* GP6_13(BKUP_TRG) */
#define GPIO_BKUP_REQB_SHIFT_CONDOR 1U /* GP3_1 (BKUP_REQB) */
#define GPIO_BKUP_TRG_SHIFT_CONDOR 0U /* GP3_0 (BKUP_TRG) */
#if DRAM_BACKUP_GPIO_USE == 1
#define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U) /* GP1_9 (BKUP_REQB) */
#define GPIO_BKUP_REQB_SHIFT_EBISU (14U) /* GP6_14(BKUP_REQB) */
#define GPIO_BKUP_REQB_SHIFT_CONDOR (1U) /* GP3_1 (BKUP_REQB) */
#endif
#define GPIO_BKUP_TRG_SHIFT_SALVATOR (8U) /* GP1_8 (BKUP_TRG) */
#define GPIO_BKUP_TRG_SHIFT_EBISU (13U) /* GP6_13(BKUP_TRG) */
#define GPIO_BKUP_TRG_SHIFT_CONDOR (0U) /* GP3_0 (BKUP_TRG) */
#define DRAM_BKUP_TRG_LOOP_CNT (1000U)
#define DRAM_BKUP_TRG_LOOP_CNT 1000U
#endif
void rcar_dram_get_boot_status(uint32_t * status)
void rcar_dram_get_boot_status(uint32_t *status)
{
#if RCAR_SYSTEM_SUSPEND
uint32_t reg_data;
uint32_t product;
uint32_t shift;
@ -62,11 +54,10 @@ void rcar_dram_get_boot_status(uint32_t * status)
}
reg_data = mmio_read_32(gpio);
if (0U != (reg_data & ((uint32_t)1U << shift))) {
if (reg_data & BIT(shift))
*status = DRAM_BOOT_STATUS_WARM;
} else {
else
*status = DRAM_BOOT_STATUS_COLD;
}
#else /* RCAR_SYSTEM_SUSPEND */
*status = DRAM_BOOT_STATUS_COLD;
#endif /* RCAR_SYSTEM_SUSPEND */
@ -116,55 +107,55 @@ int32_t rcar_dram_update_boot_status(uint32_t status)
}
if (status == DRAM_BOOT_STATUS_WARM) {
#if DRAM_BACKUP_GPIO_USE==1
mmio_setbits_32(outd, 1U << reqb);
#if DRAM_BACKUP_GPIO_USE == 1
mmio_setbits_32(outd, BIT(reqb));
#else
#if PMIC_ROHM_BD9571
/* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */
i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR,
PMIC_BKUP_MODE_CNT, &bkup_mode_cnt);
if (0 != i2c_dvfs_ret) {
PMIC_BKUP_MODE_CNT,
&bkup_mode_cnt);
if (i2c_dvfs_ret) {
ERROR("BKUP mode cnt READ ERROR.\n");
ret = DRAM_UPDATE_STATUS_ERR;
} else {
bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT;
i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
PMIC_BKUP_MODE_CNT, bkup_mode_cnt);
if (0 != i2c_dvfs_ret) {
ERROR("BKUP mode cnt WRITE ERROR. "
"value = %d\n", bkup_mode_cnt);
PMIC_BKUP_MODE_CNT,
bkup_mode_cnt);
if (i2c_dvfs_ret) {
ERROR("BKUP mode cnt WRITE ERROR. value = %d\n",
bkup_mode_cnt);
ret = DRAM_UPDATE_STATUS_ERR;
}
}
#endif /* PMIC_ROHM_BD9571 */
#endif /* DRAM_BACKUP_GPIO_USE==1 */
#endif /* DRAM_BACKUP_GPIO_USE == 1 */
/* Wait BKUP_TRG=Low */
loop_count = DRAM_BKUP_TRG_LOOP_CNT;
while (0U < loop_count) {
while (loop_count > 0) {
reg_data = mmio_read_32(gpio);
if ((reg_data &
((uint32_t)1U << trg)) == 0U) {
if (!(reg_data & BIT(trg)))
break;
}
loop_count--;
}
if (0U == loop_count) {
ERROR( "\nWarm booting...\n" \
" The potential of BKUP_TRG did not switch " \
"to Low.\n If you expect the operation of " \
"cold boot,\n check the board configuration" \
" (ex, Dip-SW) and/or the H/W failure.\n");
if (!loop_count) {
ERROR("\nWarm booting...\n"
" The potential of BKUP_TRG did not switch to Low.\n"
" If you expect the operation of cold boot,\n"
" check the board configuration (ex, Dip-SW) and/or the H/W failure.\n");
ret = DRAM_UPDATE_STATUS_ERR;
}
}
#if PMIC_ROHM_BD9571
if(0 == ret) {
qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
if (!ret) {
qllm_cnt = BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN;
i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
PMIC_QLLM_CNT, qllm_cnt);
if (0 != i2c_dvfs_ret) {
ERROR("QLLM cnt WRITE ERROR. "
"value = %d\n", qllm_cnt);
PMIC_QLLM_CNT,
qllm_cnt);
if (i2c_dvfs_ret) {
ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm_cnt);
ret = DRAM_UPDATE_STATUS_ERR;
}
}

10
drivers/staging/renesas/rcar/ddr/dram_sub_func.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,11 +7,11 @@
#ifndef DRAM_SUB_FUNC_H
#define DRAM_SUB_FUNC_H
#define DRAM_UPDATE_STATUS_ERR (-1)
#define DRAM_BOOT_STATUS_COLD (0)
#define DRAM_BOOT_STATUS_WARM (1)
#define DRAM_UPDATE_STATUS_ERR -1
#define DRAM_BOOT_STATUS_COLD 0
#define DRAM_BOOT_STATUS_WARM 1
int32_t rcar_dram_update_boot_status(uint32_t status);
void rcar_dram_get_boot_status(uint32_t * status);
void rcar_dram_get_boot_status(uint32_t *status);
#endif /* DRAM_SUB_FUNC_H */

12
plat/renesas/rcar/include/rcar_def.h
View File

@ -267,11 +267,15 @@
#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
/* for SuspendToRAM */
#define GPIO_BASE (0xE6050000U)
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
#define GPIO_BASE (0xE6050000U)
#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
#define RCAR_COLD_BOOT (0x00U)
#define RCAR_WARM_BOOT (0x01U)
#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
#define RCAR_COLD_BOOT (0x00U)
#define RCAR_WARM_BOOT (0x01U)
#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
#define KEEP10_MAGIC (0x55U)
#endif