rcar_get3: drivers: ddr: Clean up common code
Do minor coding style changes to the common DDR init code to make it checkpatch compliant and move macros out into rcar_def.h. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I67eadf8099e4ff8702105c9e07b13f308d9dbe3d
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,10 +9,10 @@
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extern int32_t rcar_dram_init(void);
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#define INITDRAM_OK (0)
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#define INITDRAM_NG (0xffffffff)
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#define INITDRAM_ERR_I (0xffffffff)
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#define INITDRAM_ERR_O (0xfffffffe)
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#define INITDRAM_ERR_T (0xfffffff0)
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#define INITDRAM_OK 0
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#define INITDRAM_NG 0xffffffff
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#define INITDRAM_ERR_I 0xffffffff
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#define INITDRAM_ERR_O 0xfffffffe
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#define INITDRAM_ERR_T 0xfffffff0
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#endif /* BOOT_INIT_DRAM_H */
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@ -12,38 +12,30 @@
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#if RCAR_SYSTEM_SUSPEND
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/* Local defines */
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#define DRAM_BACKUP_GPIO_USE (0)
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#define DRAM_BACKUP_GPIO_USE 0
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#include "iic_dvfs.h"
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#if PMIC_ROHM_BD9571
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#define PMIC_SLAVE_ADDR (0x30U)
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#define PMIC_BKUP_MODE_CNT (0x20U)
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#define PMIC_QLLM_CNT (0x27U)
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#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U))
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#define BIT_QLLM_DDR0_EN ((uint8_t)(1U << 0U))
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#define BIT_QLLM_DDR1_EN ((uint8_t)(1U << 1U))
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#define PMIC_SLAVE_ADDR 0x30U
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#define PMIC_BKUP_MODE_CNT 0x20U
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#define PMIC_QLLM_CNT 0x27U
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#define BIT_BKUP_CTRL_OUT BIT(4)
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#define BIT_QLLM_DDR0_EN BIT(0)
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#define BIT_QLLM_DDR1_EN BIT(1)
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#endif
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#define GPIO_OUTDT1 (0xE6051008U)
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#define GPIO_OUTDT3 (0xE6053008U)
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#define GPIO_INDT3 (0xE605300CU)
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#define GPIO_OUTDT6 (0xE6055408U)
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#define GPIO_BKUP_REQB_SHIFT_SALVATOR 9U /* GP1_9 (BKUP_REQB) */
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#define GPIO_BKUP_TRG_SHIFT_SALVATOR 8U /* GP1_8 (BKUP_TRG) */
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#define GPIO_BKUP_REQB_SHIFT_EBISU 14U /* GP6_14(BKUP_REQB) */
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#define GPIO_BKUP_TRG_SHIFT_EBISU 13U /* GP6_13(BKUP_TRG) */
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#define GPIO_BKUP_REQB_SHIFT_CONDOR 1U /* GP3_1 (BKUP_REQB) */
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#define GPIO_BKUP_TRG_SHIFT_CONDOR 0U /* GP3_0 (BKUP_TRG) */
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#if DRAM_BACKUP_GPIO_USE == 1
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#define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U) /* GP1_9 (BKUP_REQB) */
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#define GPIO_BKUP_REQB_SHIFT_EBISU (14U) /* GP6_14(BKUP_REQB) */
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#define GPIO_BKUP_REQB_SHIFT_CONDOR (1U) /* GP3_1 (BKUP_REQB) */
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#endif
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#define GPIO_BKUP_TRG_SHIFT_SALVATOR (8U) /* GP1_8 (BKUP_TRG) */
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#define GPIO_BKUP_TRG_SHIFT_EBISU (13U) /* GP6_13(BKUP_TRG) */
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#define GPIO_BKUP_TRG_SHIFT_CONDOR (0U) /* GP3_0 (BKUP_TRG) */
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#define DRAM_BKUP_TRG_LOOP_CNT (1000U)
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#define DRAM_BKUP_TRG_LOOP_CNT 1000U
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#endif
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void rcar_dram_get_boot_status(uint32_t * status)
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void rcar_dram_get_boot_status(uint32_t *status)
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{
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#if RCAR_SYSTEM_SUSPEND
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uint32_t reg_data;
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uint32_t product;
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uint32_t shift;
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@ -62,11 +54,10 @@ void rcar_dram_get_boot_status(uint32_t * status)
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}
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reg_data = mmio_read_32(gpio);
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if (0U != (reg_data & ((uint32_t)1U << shift))) {
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if (reg_data & BIT(shift))
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*status = DRAM_BOOT_STATUS_WARM;
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} else {
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else
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*status = DRAM_BOOT_STATUS_COLD;
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}
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#else /* RCAR_SYSTEM_SUSPEND */
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*status = DRAM_BOOT_STATUS_COLD;
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#endif /* RCAR_SYSTEM_SUSPEND */
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@ -116,55 +107,55 @@ int32_t rcar_dram_update_boot_status(uint32_t status)
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}
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if (status == DRAM_BOOT_STATUS_WARM) {
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#if DRAM_BACKUP_GPIO_USE==1
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mmio_setbits_32(outd, 1U << reqb);
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#if DRAM_BACKUP_GPIO_USE == 1
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mmio_setbits_32(outd, BIT(reqb));
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#else
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#if PMIC_ROHM_BD9571
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/* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */
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i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR,
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PMIC_BKUP_MODE_CNT, &bkup_mode_cnt);
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if (0 != i2c_dvfs_ret) {
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PMIC_BKUP_MODE_CNT,
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&bkup_mode_cnt);
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if (i2c_dvfs_ret) {
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ERROR("BKUP mode cnt READ ERROR.\n");
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ret = DRAM_UPDATE_STATUS_ERR;
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} else {
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bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT;
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i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
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PMIC_BKUP_MODE_CNT, bkup_mode_cnt);
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if (0 != i2c_dvfs_ret) {
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ERROR("BKUP mode cnt WRITE ERROR. "
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"value = %d\n", bkup_mode_cnt);
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PMIC_BKUP_MODE_CNT,
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bkup_mode_cnt);
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if (i2c_dvfs_ret) {
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ERROR("BKUP mode cnt WRITE ERROR. value = %d\n",
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bkup_mode_cnt);
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ret = DRAM_UPDATE_STATUS_ERR;
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}
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}
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#endif /* PMIC_ROHM_BD9571 */
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#endif /* DRAM_BACKUP_GPIO_USE==1 */
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#endif /* DRAM_BACKUP_GPIO_USE == 1 */
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/* Wait BKUP_TRG=Low */
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loop_count = DRAM_BKUP_TRG_LOOP_CNT;
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while (0U < loop_count) {
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while (loop_count > 0) {
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reg_data = mmio_read_32(gpio);
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if ((reg_data &
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((uint32_t)1U << trg)) == 0U) {
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if (!(reg_data & BIT(trg)))
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break;
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}
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loop_count--;
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}
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if (0U == loop_count) {
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ERROR( "\nWarm booting...\n" \
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" The potential of BKUP_TRG did not switch " \
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"to Low.\n If you expect the operation of " \
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"cold boot,\n check the board configuration" \
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" (ex, Dip-SW) and/or the H/W failure.\n");
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if (!loop_count) {
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ERROR("\nWarm booting...\n"
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" The potential of BKUP_TRG did not switch to Low.\n"
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" If you expect the operation of cold boot,\n"
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" check the board configuration (ex, Dip-SW) and/or the H/W failure.\n");
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ret = DRAM_UPDATE_STATUS_ERR;
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}
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}
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#if PMIC_ROHM_BD9571
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if(0 == ret) {
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qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
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if (!ret) {
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qllm_cnt = BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN;
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i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
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PMIC_QLLM_CNT, qllm_cnt);
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if (0 != i2c_dvfs_ret) {
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ERROR("QLLM cnt WRITE ERROR. "
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"value = %d\n", qllm_cnt);
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PMIC_QLLM_CNT,
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qllm_cnt);
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if (i2c_dvfs_ret) {
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ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm_cnt);
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ret = DRAM_UPDATE_STATUS_ERR;
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}
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}
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/*
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* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DRAM_SUB_FUNC_H
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#define DRAM_SUB_FUNC_H
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#define DRAM_UPDATE_STATUS_ERR (-1)
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#define DRAM_BOOT_STATUS_COLD (0)
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#define DRAM_BOOT_STATUS_WARM (1)
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#define DRAM_UPDATE_STATUS_ERR -1
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#define DRAM_BOOT_STATUS_COLD 0
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#define DRAM_BOOT_STATUS_WARM 1
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int32_t rcar_dram_update_boot_status(uint32_t status);
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void rcar_dram_get_boot_status(uint32_t * status);
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void rcar_dram_get_boot_status(uint32_t *status);
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#endif /* DRAM_SUB_FUNC_H */
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#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
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#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
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/* for SuspendToRAM */
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#define GPIO_BASE (0xE6050000U)
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#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
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#define GPIO_BASE (0xE6050000U)
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#define GPIO_INDT1 (GPIO_BASE + 0x100CU)
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#define GPIO_INDT3 (GPIO_BASE + 0x300CU)
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#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
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#define RCAR_COLD_BOOT (0x00U)
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#define RCAR_WARM_BOOT (0x01U)
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#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U)
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#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U)
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#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
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#define RCAR_COLD_BOOT (0x00U)
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#define RCAR_WARM_BOOT (0x01U)
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#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
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#define KEEP10_MAGIC (0x55U)
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#endif
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