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Merge pull request #1699 from chandnich/sgi-mt-support 

Add support to implement multi-threaded platforms for SGI
This commit is contained in:
Soby Mathew 2018-12-03 13:29:33 +00:00 committed by GitHub
parent 500db01352 a83d4bd765
commit 41771df849
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GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 28 additions and 5 deletions
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1
include/plat/arm/common/arm_def.h
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@ -34,6 +34,7 @@
#define ARM_PWR_LVL0 MPIDR_AFFLVL0
#define ARM_PWR_LVL1 MPIDR_AFFLVL1
#define ARM_PWR_LVL2 MPIDR_AFFLVL2
#define ARM_PWR_LVL3 MPIDR_AFFLVL3
/*
* Macros for local power states in ARM platforms encoded by State-ID field

3
include/plat/arm/css/common/css_pm.h
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@ -11,9 +11,6 @@
#include <psci.h>
#include <stdint.h>
/* System power domain at level 2, as currently implemented by CSS platforms */
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
/* Macros to read the CSS power domain state */
#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]

3
plat/arm/board/juno/include/platform_def.h
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@ -295,4 +295,7 @@
#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
#define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS
/* System power domain level */
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#endif /* PLATFORM_DEF_H */

2
plat/arm/board/n1sdp/include/platform_def.h
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@ -32,6 +32,8 @@
N1SDP_MAX_CPUS_PER_CLUSTER * \
N1SDP_MAX_PE_PER_CPU)
/* System power domain level */
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the

5
plat/arm/board/sgi575/include/platform_def.h
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@ -20,4 +20,9 @@
#define SGI575_DMC620_BASE0 UL(0x4e000000)
#define SGI575_DMC620_BASE1 UL(0x4e100000)
/* System power domain level */
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
#endif /* PLATFORM_DEF_H */

5
plat/arm/board/sgiclarka/include/platform_def.h
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@ -20,4 +20,9 @@
#define SGICLARKA_DMC620_BASE0 UL(0x4e000000)
#define SGICLARKA_DMC620_BASE1 UL(0x4e100000)
/* System power domain level */
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
#endif /* PLATFORM_DEF_H */

2
plat/arm/css/sgi/include/sgi_base_platform_def.h
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@ -119,8 +119,6 @@
#define PLAT_ARM_NSRAM_BASE 0x06000000
#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */
#define PLAT_MAX_PWR_LVL U(1)
#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)

8
plat/arm/css/sgi/sgi_topology.c
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@ -44,3 +44,11 @@ const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[32] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
};
/******************************************************************************
* Return the number of PE's supported by the CPU.
*****************************************************************************/
unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr)
{
return CSS_SGI_MAX_PE_PER_CPU;
}

4
plat/arm/css/sgm/include/sgm_base_platform_def.h
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@ -239,4 +239,8 @@
*/
#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
/* System power domain level */
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#endif /* SGM_BASE_PLATFORM_DEF_H */