commit
429421de82
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@ -207,15 +207,17 @@ bits.
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#### Platform initialization
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#### Platform initialization
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BL2 does not perform any platform initialization that affects subsequent
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BL2 copies the information regarding the trusted SRAM populated by BL1 using a
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stages of the ARM Trusted Firmware or normal world software. It copies the
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information regarding the trusted SRAM populated by BL1 using a
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platform-specific mechanism. It calculates the limits of DRAM (main memory)
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platform-specific mechanism. It calculates the limits of DRAM (main memory)
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to determine whether there is enough space to load the BL3-3 image. A platform
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to determine whether there is enough space to load the BL3-3 image. A platform
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defined base address is used to specify the load address for the BL3-1 image.
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defined base address is used to specify the load address for the BL3-1 image.
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It also defines the extents of memory available for use by the BL3-2 image.
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It also defines the extents of memory available for use by the BL3-2 image.
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BL2 also initializes UART0 (PL011 console), which enables access to the
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BL2 also initializes UART0 (PL011 console), which enables access to the
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`printf` family of functions in BL2
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`printf` family of functions in BL2. Platform security is initialized to allow
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access to access controlled components. On the Base FVP a TrustZone controller
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(TZC-400) is configured to give full access to the platform DRAM. The storage
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abstraction layer is initialized which is used to load further bootloader
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images.
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#### BL3-1 (EL3 Runtime Firmware) image load
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#### BL3-1 (EL3 Runtime Firmware) image load
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@ -630,6 +630,10 @@ The non-secure memory extents used for loading BL3-3 are also initialized in
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this function. This information is accessible in the `bl33_meminfo` field in
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this function. This information is accessible in the `bl33_meminfo` field in
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the `bl31_args` structure pointed to by `bl2_to_bl31_args`.
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the `bl31_args` structure pointed to by `bl2_to_bl31_args`.
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Platform security components are configured if required. For the Base FVP the
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TZC-400 TrustZone controller is configured to grant secure and non-secure access
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to DRAM.
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This function is also responsible for initializing the storage abstraction layer
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This function is also responsible for initializing the storage abstraction layer
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which is used to load further bootloader images.
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which is used to load further bootloader images.
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@ -532,9 +532,15 @@ NOTE: The `-C bp.flashloader0.fname` parameter is used to load a Firmware Image
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Package at the start of NOR FLASH0 (see the "Building the Trusted Firmware"
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Package at the start of NOR FLASH0 (see the "Building the Trusted Firmware"
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section above).
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section above).
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NOTE: Setting the `-C bp.secure_memory` parameter to `1` is only supported on
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FVP versions 5.4 and newer. Setting this parameter to `0` is also supported.
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The `-C bp.tzc_400.diagnostics=1` parameter is optional. It instructs the FVP to
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provide some helpful information if a secure memory violation occurs.
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<path-to>/FVP_Base_AEMv8A-AEMv8A \
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<path-to>/FVP_Base_AEMv8A-AEMv8A \
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-C pctl.startup=0.0.0.0 \
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-C pctl.startup=0.0.0.0 \
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-C bp.secure_memory=0 \
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cluster0.NUM_CORES=4 \
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-C cluster0.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cache_state_modelled=1 \
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-C cache_state_modelled=1 \
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@ -560,9 +566,15 @@ NOTE: The `-C bp.flashloader0.fname` parameter is used to load a Firmware Image
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Package at the start of NOR FLASH0 (see the "Building the Trusted Firmware"
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Package at the start of NOR FLASH0 (see the "Building the Trusted Firmware"
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section above).
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section above).
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NOTE: Setting the `-C bp.secure_memory` parameter to `1` is only supported on
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FVP versions 5.4 and newer. Setting this parameter to `0` is also supported.
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The `-C bp.tzc_400.diagnostics=1` parameter is optional. It instructs the FVP to
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provide some helpful information if a secure memory violation occurs.
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<path-to>/FVP_Base_Cortex-A57x4-A53x4 \
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<path-to>/FVP_Base_Cortex-A57x4-A53x4 \
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-C pctl.startup=0.0.0.0 \
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-C pctl.startup=0.0.0.0 \
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-C bp.secure_memory=0 \
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cache_state_modelled=1 \
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-C cache_state_modelled=1 \
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-C bp.pl011_uart0.untimed_fifos=1 \
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-C bp.pl011_uart0.untimed_fifos=1 \
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-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
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-C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
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@ -0,0 +1,265 @@
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/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include "arch_helpers.h"
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#include "tzc400.h"
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#include "mmio.h"
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#include "debug.h"
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static uint32_t tzc_read_build_config(uint64_t base)
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{
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return mmio_read_32(base + BUILD_CONFIG_OFF);
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}
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static uint32_t tzc_read_gate_keeper(uint64_t base)
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{
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return mmio_read_32(base + GATE_KEEPER_OFF);
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}
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static void tzc_write_gate_keeper(uint64_t base, uint32_t val)
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{
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mmio_write_32(base + GATE_KEEPER_OFF, val);
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}
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static void tzc_write_action(uint64_t base, enum tzc_action action)
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{
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mmio_write_32(base + ACTION_OFF, action);
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}
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static void tzc_write_region_base_low(uint64_t base, uint32_t region, uint32_t val)
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{
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mmio_write_32(base + REGION_BASE_LOW_OFF + REGION_NUM_OFF(region), val);
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}
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static void tzc_write_region_base_high(uint64_t base, uint32_t region, uint32_t val)
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{
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mmio_write_32(base + REGION_BASE_HIGH_OFF + REGION_NUM_OFF(region), val);
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}
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static void tzc_write_region_top_low(uint64_t base, uint32_t region, uint32_t val)
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{
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mmio_write_32(base + REGION_TOP_LOW_OFF + REGION_NUM_OFF(region), val);
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}
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static void tzc_write_region_top_high(uint64_t base, uint32_t region, uint32_t val)
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{
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mmio_write_32(base + REGION_TOP_HIGH_OFF + REGION_NUM_OFF(region), val);
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}
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static void tzc_write_region_attributes(uint64_t base, uint32_t region, uint32_t val)
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{
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mmio_write_32(base + REGION_ATTRIBUTES_OFF + REGION_NUM_OFF(region), val);
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}
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static void tzc_write_region_id_access(uint64_t base, uint32_t region, uint32_t val)
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{
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mmio_write_32(base + REGION_ID_ACCESS_OFF + REGION_NUM_OFF(region), val);
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}
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static uint32_t tzc_read_component_id(uint64_t base)
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{
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uint32_t id;
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id = mmio_read_8(base + CID0_OFF);
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id |= (mmio_read_8(base + CID1_OFF) << 8);
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id |= (mmio_read_8(base + CID2_OFF) << 16);
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id |= (mmio_read_8(base + CID3_OFF) << 24);
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return id;
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}
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static uint32_t tzc_get_gate_keeper(uint64_t base, uint8_t filter)
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{
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uint32_t tmp;
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tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) &
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GATE_KEEPER_OS_MASK;
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return tmp >> filter;
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}
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/* This function is not MP safe. */
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static void tzc_set_gate_keeper(uint64_t base, uint8_t filter, uint32_t val)
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{
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uint32_t tmp;
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/* Upper half is current state. Lower half is requested state. */
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tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) &
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GATE_KEEPER_OS_MASK;
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if (val)
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tmp |= (1 << filter);
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else
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tmp &= ~(1 << filter);
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tzc_write_gate_keeper(base, (tmp & GATE_KEEPER_OR_MASK) <<
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GATE_KEEPER_OR_SHIFT);
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/* Wait here until we see the change reflected in the TZC status. */
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while (((tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) &
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GATE_KEEPER_OS_MASK) != tmp)
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;
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}
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void tzc_init(struct tzc_instance *controller)
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{
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uint32_t tzc_id, tzc_build;
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assert(controller != NULL);
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/*
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* We expect to see a tzc400. Check component ID. The TZC-400 TRM shows
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* component ID is expected to be "0xB105F00D".
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*/
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tzc_id = tzc_read_component_id(controller->base);
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if (tzc_id != TZC400_COMPONENT_ID) {
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ERROR("TZC : Wrong device ID (0x%x).\n", tzc_id);
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panic();
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}
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/* Save values we will use later. */
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tzc_build = tzc_read_build_config(controller->base);
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controller->num_filters = ((tzc_build >> BUILD_CONFIG_NF_SHIFT) &
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BUILD_CONFIG_NF_MASK) + 1;
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controller->addr_width = ((tzc_build >> BUILD_CONFIG_AW_SHIFT) &
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BUILD_CONFIG_AW_MASK) + 1;
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controller->num_regions = ((tzc_build >> BUILD_CONFIG_NR_SHIFT) &
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BUILD_CONFIG_NR_MASK) + 1;
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}
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/*
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* `tzc_configure_region` is used to program regions into the TrustZone
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* controller. A region can be associated with more than one filter. The
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* associated filters are passed in as a bitmap (bit0 = filter0).
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* NOTE:
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* The region 0 covers the whole address space and is enabled on all filters,
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* this cannot be changed. It is, however, possible to change some region 0
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* permissions.
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*/
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void tzc_configure_region(const struct tzc_instance *controller,
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uint32_t filters,
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uint8_t region,
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uint64_t region_base,
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uint64_t region_top,
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enum tzc_region_attributes sec_attr,
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uint32_t ns_device_access)
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{
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uint64_t max_addr;
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assert(controller != NULL);
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/* Do range checks on filters and regions. */
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assert(((filters >> controller->num_filters) == 0) &&
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(region < controller->num_regions));
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/*
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* Do address range check based on TZC configuration. A 64bit address is
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* the max and expected case.
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|
*/
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max_addr = UINT64_MAX >> (64 - controller->addr_width);
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if ((region_top > max_addr) || (region_base >= region_top))
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assert(0);
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/* region_base and (region_top + 1) must be 4KB aligned */
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assert(((region_base | (region_top + 1)) & (4096 - 1)) == 0);
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|
assert(sec_attr <= TZC_REGION_S_RDWR);
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||||||
|
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||||||
|
/*
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|
* Inputs look ok, start programming registers.
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|
* All the address registers are 32 bits wide and have a LOW and HIGH
|
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|
* component used to construct a up to a 64bit address.
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|
*/
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tzc_write_region_base_low(controller->base, region, (uint32_t)(region_base));
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tzc_write_region_base_high(controller->base, region, (uint32_t)(region_base >> 32));
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tzc_write_region_top_low(controller->base, region, (uint32_t)(region_top));
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tzc_write_region_top_high(controller->base, region, (uint32_t)(region_top >> 32));
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/* Assign the region to a filter and set secure attributes */
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tzc_write_region_attributes(controller->base, region,
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(sec_attr << REGION_ATTRIBUTES_SEC_SHIFT) | filters);
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||||||
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|
/*
|
||||||
|
* Specify which non-secure devices have permission to access this
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|
* region.
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||||||
|
*/
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|
tzc_write_region_id_access(controller->base, region, ns_device_access);
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|
}
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|
||||||
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||||||
|
void tzc_set_action(const struct tzc_instance *controller, enum tzc_action action)
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||||||
|
{
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||||||
|
assert(controller != NULL);
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||||||
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|
||||||
|
/*
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||||||
|
* - Currently no handler is provided to trap an error via interrupt
|
||||||
|
* or exception.
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|
* - The interrupt action has not been tested.
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||||||
|
*/
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||||||
|
tzc_write_action(controller->base, action);
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||||||
|
}
|
||||||
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||||||
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|
||||||
|
void tzc_enable_filters(const struct tzc_instance *controller)
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||||||
|
{
|
||||||
|
uint32_t state;
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||||||
|
uint32_t filter;
|
||||||
|
|
||||||
|
assert(controller != NULL);
|
||||||
|
|
||||||
|
for (filter = 0; filter < controller->num_filters; filter++) {
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|
state = tzc_get_gate_keeper(controller->base, filter);
|
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|
if (state) {
|
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|
ERROR("TZC : Filter %d Gatekeeper already enabled.\n",
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|
filter);
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|
panic();
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|
}
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|
tzc_set_gate_keeper(controller->base, filter, 1);
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||||||
|
}
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||||||
|
}
|
||||||
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|
||||||
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|
||||||
|
void tzc_disable_filters(const struct tzc_instance *controller)
|
||||||
|
{
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||||||
|
uint32_t filter;
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||||||
|
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||||||
|
assert(controller != NULL);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We don't do the same state check as above as the Gatekeepers are
|
||||||
|
* disabled after reset.
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||||||
|
*/
|
||||||
|
for (filter = 0; filter < controller->num_filters; filter++)
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||||||
|
tzc_set_gate_keeper(controller->base, filter, 0);
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||||||
|
}
|
|
@ -0,0 +1,211 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
* list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
* to endorse or promote products derived from this software without specific
|
||||||
|
* prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __TZC400_H__
|
||||||
|
#define __TZC400_H__
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#define BUILD_CONFIG_OFF 0x000
|
||||||
|
#define ACTION_OFF 0x004
|
||||||
|
#define GATE_KEEPER_OFF 0x008
|
||||||
|
#define SPECULATION_CTRL_OFF 0x00c
|
||||||
|
#define INT_STATUS 0x010
|
||||||
|
#define INT_CLEAR 0x014
|
||||||
|
|
||||||
|
#define FAIL_ADDRESS_LOW_OFF 0x020
|
||||||
|
#define FAIL_ADDRESS_HIGH_OFF 0x024
|
||||||
|
#define FAIL_CONTROL_OFF 0x028
|
||||||
|
#define FAIL_ID 0x02c
|
||||||
|
|
||||||
|
#define REGION_BASE_LOW_OFF 0x100
|
||||||
|
#define REGION_BASE_HIGH_OFF 0x104
|
||||||
|
#define REGION_TOP_LOW_OFF 0x108
|
||||||
|
#define REGION_TOP_HIGH_OFF 0x10c
|
||||||
|
#define REGION_ATTRIBUTES_OFF 0x110
|
||||||
|
#define REGION_ID_ACCESS_OFF 0x114
|
||||||
|
#define REGION_NUM_OFF(region) (0x20 * region)
|
||||||
|
|
||||||
|
/* ID Registers */
|
||||||
|
#define PID0_OFF 0xfe0
|
||||||
|
#define PID1_OFF 0xfe4
|
||||||
|
#define PID2_OFF 0xfe8
|
||||||
|
#define PID3_OFF 0xfec
|
||||||
|
#define PID4_OFF 0xfd0
|
||||||
|
#define PID5_OFF 0xfd4
|
||||||
|
#define PID6_OFF 0xfd8
|
||||||
|
#define PID7_OFF 0xfdc
|
||||||
|
#define CID0_OFF 0xff0
|
||||||
|
#define CID1_OFF 0xff4
|
||||||
|
#define CID2_OFF 0xff8
|
||||||
|
#define CID3_OFF 0xffc
|
||||||
|
|
||||||
|
#define BUILD_CONFIG_NF_SHIFT 24
|
||||||
|
#define BUILD_CONFIG_NF_MASK 0x3
|
||||||
|
#define BUILD_CONFIG_AW_SHIFT 8
|
||||||
|
#define BUILD_CONFIG_AW_MASK 0x3f
|
||||||
|
#define BUILD_CONFIG_NR_SHIFT 0
|
||||||
|
#define BUILD_CONFIG_NR_MASK 0x1f
|
||||||
|
|
||||||
|
/* Not describing the case where regions 1 to 8 overlap */
|
||||||
|
#define ACTION_RV_SHIFT 0
|
||||||
|
#define ACTION_RV_MASK 0x3
|
||||||
|
#define ACTION_RV_LOWOK 0x0
|
||||||
|
#define ACTION_RV_LOWERR 0x1
|
||||||
|
#define ACTION_RV_HIGHOK 0x2
|
||||||
|
#define ACTION_RV_HIGHERR 0x3
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Number of gate keepers is implementation defined. But we know the max for
|
||||||
|
* this device is 4. Get implementation details from BUILD_CONFIG.
|
||||||
|
*/
|
||||||
|
#define GATE_KEEPER_OS_SHIFT 16
|
||||||
|
#define GATE_KEEPER_OS_MASK 0xf
|
||||||
|
#define GATE_KEEPER_OR_SHIFT 0
|
||||||
|
#define GATE_KEEPER_OR_MASK 0xf
|
||||||
|
|
||||||
|
/* Speculation is enabled by default. */
|
||||||
|
#define SPECULATION_CTRL_WRITE_DISABLE (1 << 1)
|
||||||
|
#define SPECULATION_CTRL_READ_DISABLE (1 << 0)
|
||||||
|
|
||||||
|
/* Max number of filters allowed is 4. */
|
||||||
|
#define INT_STATUS_OVERLAP_SHIFT 16
|
||||||
|
#define INT_STATUS_OVERLAP_MASK 0xf
|
||||||
|
#define INT_STATUS_OVERRUN_SHIFT 8
|
||||||
|
#define INT_STATUS_OVERRUN_MASK 0xf
|
||||||
|
#define INT_STATUS_STATUS_SHIFT 0
|
||||||
|
#define INT_STATUS_STATUS_MASK 0xf
|
||||||
|
|
||||||
|
#define INT_CLEAR_CLEAR_SHIFT 0
|
||||||
|
#define INT_CLEAR_CLEAR_MASK 0xf
|
||||||
|
|
||||||
|
#define FAIL_CONTROL_DIR_SHIFT (1 << 24)
|
||||||
|
#define FAIL_CONTROL_DIR_READ 0x0
|
||||||
|
#define FAIL_CONTROL_DIR_WRITE 0x1
|
||||||
|
#define FAIL_CONTROL_NS_SHIFT (1 << 21)
|
||||||
|
#define FAIL_CONTROL_NS_SECURE 0x0
|
||||||
|
#define FAIL_CONTROL_NS_NONSECURE 0x1
|
||||||
|
#define FAIL_CONTROL_PRIV_SHIFT (1 << 20)
|
||||||
|
#define FAIL_CONTROL_PRIV_PRIV 0x0
|
||||||
|
#define FAIL_CONTROL_PRIV_UNPRIV 0x1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.
|
||||||
|
* Platform should provide the value on initialisation.
|
||||||
|
*/
|
||||||
|
#define FAIL_ID_VNET_SHIFT 24
|
||||||
|
#define FAIL_ID_VNET_MASK 0xf
|
||||||
|
#define FAIL_ID_ID_SHIFT 0
|
||||||
|
|
||||||
|
/* Used along with 'tzc_region_attributes_t' below */
|
||||||
|
#define REGION_ATTRIBUTES_SEC_SHIFT 30
|
||||||
|
#define REGION_ATTRIBUTES_F_EN_SHIFT 0
|
||||||
|
#define REGION_ATTRIBUTES_F_EN_MASK 0xf
|
||||||
|
|
||||||
|
#define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16
|
||||||
|
#define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0
|
||||||
|
#define REGION_ID_ACCESS_NSAID_ID_MASK 0xf
|
||||||
|
|
||||||
|
|
||||||
|
/* Macros for setting Region ID access permissions based on NSAID */
|
||||||
|
#define TZC_REGION_ACCESS_RD(id) \
|
||||||
|
((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \
|
||||||
|
REGION_ID_ACCESS_NSAID_RD_EN_SHIFT)
|
||||||
|
#define TZC_REGION_ACCESS_WR(id) \
|
||||||
|
((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \
|
||||||
|
REGION_ID_ACCESS_NSAID_WR_EN_SHIFT)
|
||||||
|
#define TZC_REGION_ACCESS_RDWR(id) \
|
||||||
|
(TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id))
|
||||||
|
|
||||||
|
/* Filters are bit mapped 0 to 3. */
|
||||||
|
#define TZC400_COMPONENT_ID 0xb105f00d
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Function & variable prototypes
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* What type of action is expected when an access violation occurs.
|
||||||
|
* The memory requested is zeroed. But we can also raise and event to
|
||||||
|
* let the system know it happened.
|
||||||
|
* We can raise an interrupt(INT) and/or cause an exception(ERR).
|
||||||
|
* TZC_ACTION_NONE - No interrupt, no Exception
|
||||||
|
* TZC_ACTION_ERR - No interrupt, raise exception -> sync external
|
||||||
|
* data abort
|
||||||
|
* TZC_ACTION_INT - Raise interrupt, no exception
|
||||||
|
* TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync
|
||||||
|
* external data abort
|
||||||
|
*/
|
||||||
|
enum tzc_action {
|
||||||
|
TZC_ACTION_NONE = 0,
|
||||||
|
TZC_ACTION_ERR = 1,
|
||||||
|
TZC_ACTION_INT = 2,
|
||||||
|
TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT)
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Controls secure access to a region. If not enabled secure access is not
|
||||||
|
* allowed to region.
|
||||||
|
*/
|
||||||
|
enum tzc_region_attributes {
|
||||||
|
TZC_REGION_S_NONE = 0,
|
||||||
|
TZC_REGION_S_RD = 1,
|
||||||
|
TZC_REGION_S_WR = 2,
|
||||||
|
TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR)
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Implementation defined values used to validate inputs later.
|
||||||
|
* Filters : max of 4 ; 0 to 3
|
||||||
|
* Regions : max of 9 ; 0 to 8
|
||||||
|
* Address width : Values between 32 to 64
|
||||||
|
*/
|
||||||
|
struct tzc_instance {
|
||||||
|
uint64_t base;
|
||||||
|
uint32_t aid_width;
|
||||||
|
uint8_t addr_width;
|
||||||
|
uint8_t num_filters;
|
||||||
|
uint8_t num_regions;
|
||||||
|
};
|
||||||
|
|
||||||
|
void tzc_init(struct tzc_instance *controller);
|
||||||
|
void tzc_configure_region(const struct tzc_instance *controller, uint32_t filters,
|
||||||
|
uint8_t region, uint64_t region_base, uint64_t region_top,
|
||||||
|
enum tzc_region_attributes sec_attr, uint32_t ns_device_access);
|
||||||
|
void tzc_enable_filters(const struct tzc_instance *controller);
|
||||||
|
void tzc_disable_filters(const struct tzc_instance *controller);
|
||||||
|
void tzc_set_action(const struct tzc_instance *controller,
|
||||||
|
enum tzc_action action);
|
||||||
|
|
||||||
|
#endif /*__ASSEMBLY__*/
|
||||||
|
|
||||||
|
#endif /* __TZC400__ */
|
Binary file not shown.
|
@ -147,10 +147,10 @@
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
ranges;
|
ranges;
|
||||||
frame@2a820000 {
|
frame@2a830000 {
|
||||||
frame-number = <0>;
|
frame-number = <1>;
|
||||||
interrupts = <0 25 4>;
|
interrupts = <0 26 4>;
|
||||||
reg = <0x0 0x2a820000 0x0 0x10000>;
|
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
Binary file not shown.
|
@ -147,10 +147,10 @@
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
ranges;
|
ranges;
|
||||||
frame@2a820000 {
|
frame@2a830000 {
|
||||||
frame-number = <0>;
|
frame-number = <1>;
|
||||||
interrupts = <0 25 4>;
|
interrupts = <0 26 4>;
|
||||||
reg = <0x0 0x2a820000 0x0 0x10000>;
|
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
Binary file not shown.
|
@ -156,10 +156,10 @@
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
ranges;
|
ranges;
|
||||||
frame@2a820000 {
|
frame@2a830000 {
|
||||||
frame-number = <0>;
|
frame-number = <1>;
|
||||||
interrupts = <0 25 4>;
|
interrupts = <0 26 4>;
|
||||||
reg = <0x0 0x2a820000 0x0 0x10000>;
|
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
Binary file not shown.
|
@ -36,7 +36,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "FVP Base";
|
model = "FVP Foundation";
|
||||||
compatible = "arm,fvp-base", "arm,vexpress";
|
compatible = "arm,fvp-base", "arm,vexpress";
|
||||||
interrupt-parent = <&gic>;
|
interrupt-parent = <&gic>;
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
|
@ -123,10 +123,10 @@
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
ranges;
|
ranges;
|
||||||
frame@2a820000 {
|
frame@2a830000 {
|
||||||
frame-number = <0>;
|
frame-number = <1>;
|
||||||
interrupts = <0 25 4>;
|
interrupts = <0 26 4>;
|
||||||
reg = <0x0 0x2a820000 0x0 0x10000>;
|
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
Binary file not shown.
|
@ -36,7 +36,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "FVP Base";
|
model = "FVP Foundation";
|
||||||
compatible = "arm,fvp-base", "arm,vexpress";
|
compatible = "arm,fvp-base", "arm,vexpress";
|
||||||
interrupt-parent = <&gic>;
|
interrupt-parent = <&gic>;
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
|
@ -123,10 +123,10 @@
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
ranges;
|
ranges;
|
||||||
frame@2a820000 {
|
frame@2a830000 {
|
||||||
frame-number = <0>;
|
frame-number = <1>;
|
||||||
interrupts = <0 25 4>;
|
interrupts = <0 26 4>;
|
||||||
reg = <0x0 0x2a820000 0x0 0x10000>;
|
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
Binary file not shown.
|
@ -36,7 +36,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "FVP Base";
|
model = "FVP Foundation";
|
||||||
compatible = "arm,fvp-base", "arm,vexpress";
|
compatible = "arm,fvp-base", "arm,vexpress";
|
||||||
interrupt-parent = <&gic>;
|
interrupt-parent = <&gic>;
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
|
@ -132,10 +132,10 @@
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
ranges;
|
ranges;
|
||||||
frame@2a820000 {
|
frame@2a830000 {
|
||||||
frame-number = <0>;
|
frame-number = <1>;
|
||||||
interrupts = <0 25 4>;
|
interrupts = <0 26 4>;
|
||||||
reg = <0x0 0x2a820000 0x0 0x10000>;
|
reg = <0x0 0x2a830000 0x0 0x10000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -35,6 +35,9 @@
|
||||||
|
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern void mmio_write_8(uintptr_t addr, uint8_t value);
|
||||||
|
extern uint8_t mmio_read_8(uintptr_t addr);
|
||||||
|
|
||||||
extern void mmio_write_32(uintptr_t addr, uint32_t value);
|
extern void mmio_write_32(uintptr_t addr, uint32_t value);
|
||||||
extern uint32_t mmio_read_32(uintptr_t addr);
|
extern uint32_t mmio_read_32(uintptr_t addr);
|
||||||
|
|
||||||
|
|
10
lib/mmio.c
10
lib/mmio.c
|
@ -30,6 +30,16 @@
|
||||||
|
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
|
void mmio_write_8(uintptr_t addr, uint8_t value)
|
||||||
|
{
|
||||||
|
*(volatile uint8_t*)addr = value;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t mmio_read_8(uintptr_t addr)
|
||||||
|
{
|
||||||
|
return *(volatile uint8_t*)addr;
|
||||||
|
}
|
||||||
|
|
||||||
void mmio_write_32(uintptr_t addr, uint32_t value)
|
void mmio_write_32(uintptr_t addr, uint32_t value)
|
||||||
{
|
{
|
||||||
*(volatile uint32_t*)addr = value;
|
*(volatile uint32_t*)addr = value;
|
||||||
|
|
|
@ -220,6 +220,7 @@ int platform_config_setup(void)
|
||||||
platform_config[CONFIG_CPU_SETUP] = 0;
|
platform_config[CONFIG_CPU_SETUP] = 0;
|
||||||
platform_config[CONFIG_BASE_MMAP] = 0;
|
platform_config[CONFIG_BASE_MMAP] = 0;
|
||||||
platform_config[CONFIG_HAS_CCI] = 0;
|
platform_config[CONFIG_HAS_CCI] = 0;
|
||||||
|
platform_config[CONFIG_HAS_TZC] = 0;
|
||||||
break;
|
break;
|
||||||
case HBI_FVP_BASE:
|
case HBI_FVP_BASE:
|
||||||
midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
|
midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
|
||||||
|
@ -232,6 +233,7 @@ int platform_config_setup(void)
|
||||||
platform_config[CONFIG_MAX_AFF1] = 2;
|
platform_config[CONFIG_MAX_AFF1] = 2;
|
||||||
platform_config[CONFIG_BASE_MMAP] = 1;
|
platform_config[CONFIG_BASE_MMAP] = 1;
|
||||||
platform_config[CONFIG_HAS_CCI] = 1;
|
platform_config[CONFIG_HAS_CCI] = 1;
|
||||||
|
platform_config[CONFIG_HAS_TZC] = 1;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
assert(0);
|
assert(0);
|
||||||
|
|
|
@ -122,6 +122,14 @@ void bl2_early_platform_setup(meminfo *mem_layout,
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
void bl2_platform_setup()
|
void bl2_platform_setup()
|
||||||
{
|
{
|
||||||
|
/*
|
||||||
|
* Do initial security configuration to allow DRAM/device access. On
|
||||||
|
* Base FVP only DRAM security is programmable (via TrustZone), but
|
||||||
|
* other platforms might have more programmable security devices
|
||||||
|
* present.
|
||||||
|
*/
|
||||||
|
plat_security_setup();
|
||||||
|
|
||||||
/* Initialise the IO layer and register platform IO devices */
|
/* Initialise the IO layer and register platform IO devices */
|
||||||
io_setup();
|
io_setup();
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,131 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* Redistributions of source code must retain the above copyright notice, this
|
||||||
|
* list of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
* this list of conditions and the following disclaimer in the documentation
|
||||||
|
* and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
* to endorse or promote products derived from this software without specific
|
||||||
|
* prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||||
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include "platform.h"
|
||||||
|
#include "tzc400.h"
|
||||||
|
#include "debug.h"
|
||||||
|
|
||||||
|
/* Used to improve readability for configuring regions. */
|
||||||
|
#define FILTER_SHIFT(filter) (1 << filter)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For the moment we assume that all security programming is done by the
|
||||||
|
* primary core.
|
||||||
|
* TODO:
|
||||||
|
* Might want to enable interrupt on violations when supported?
|
||||||
|
*/
|
||||||
|
void plat_security_setup(void)
|
||||||
|
{
|
||||||
|
struct tzc_instance controller;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The Base FVP has a TrustZone address space controller, the Foundation
|
||||||
|
* FVP does not. Trying to program the device on the foundation FVP will
|
||||||
|
* cause an abort.
|
||||||
|
*
|
||||||
|
* If the platform had additional peripheral specific security
|
||||||
|
* configurations, those would be configured here.
|
||||||
|
*/
|
||||||
|
|
||||||
|
if (!platform_get_cfgvar(CONFIG_HAS_TZC))
|
||||||
|
return;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The TrustZone controller controls access to main DRAM. Give
|
||||||
|
* full NS access for the moment to use with OS.
|
||||||
|
*/
|
||||||
|
INFO("Configuring TrustZone Controller\n");
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The driver does some error checking and will assert.
|
||||||
|
* - Provide base address of device on platform.
|
||||||
|
* - Provide width of ACE-Lite IDs on platform.
|
||||||
|
*/
|
||||||
|
controller.base = TZC400_BASE;
|
||||||
|
controller.aid_width = FVP_AID_WIDTH;
|
||||||
|
tzc_init(&controller);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Currently only filters 0 and 2 are connected on Base FVP.
|
||||||
|
* Filter 0 : CPU clusters (no access to DRAM by default)
|
||||||
|
* Filter 1 : not connected
|
||||||
|
* Filter 2 : LCDs (access to VRAM allowed by default)
|
||||||
|
* Filter 3 : not connected
|
||||||
|
* Programming unconnected filters will have no effect at the
|
||||||
|
* moment. These filter could, however, be connected in future.
|
||||||
|
* So care should be taken not to configure the unused filters.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Disable all filters before programming. */
|
||||||
|
tzc_disable_filters(&controller);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Allow full access to all DRAM to supported devices for the
|
||||||
|
* moment. Give access to the CPUs and Virtio. Some devices
|
||||||
|
* would normally use the default ID so allow that too. We use
|
||||||
|
* three different regions to cover the three separate blocks of
|
||||||
|
* memory in the FVPs. We allow secure access to DRAM to load NS
|
||||||
|
* software.
|
||||||
|
* FIXME: In current models Virtio uses a reserved ID. This is
|
||||||
|
* not correct and will be fixed.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Set to cover 2GB block of DRAM */
|
||||||
|
tzc_configure_region(&controller, FILTER_SHIFT(0), 1,
|
||||||
|
DRAM_BASE, 0xFFFFFFFF, TZC_REGION_S_RDWR,
|
||||||
|
TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) |
|
||||||
|
TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
|
||||||
|
TZC_REGION_ACCESS_RDWR(FVP_NSAID_RES5));
|
||||||
|
|
||||||
|
/* Set to cover the 30GB block */
|
||||||
|
tzc_configure_region(&controller, FILTER_SHIFT(0), 2,
|
||||||
|
0x880000000, 0xFFFFFFFFF, TZC_REGION_S_RDWR,
|
||||||
|
TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) |
|
||||||
|
TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
|
||||||
|
TZC_REGION_ACCESS_RDWR(FVP_NSAID_RES5));
|
||||||
|
|
||||||
|
/* Set to cover 480GB block */
|
||||||
|
tzc_configure_region(&controller, FILTER_SHIFT(0), 3,
|
||||||
|
0x8800000000, 0xFFFFFFFFFF, TZC_REGION_S_RDWR,
|
||||||
|
TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) |
|
||||||
|
TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
|
||||||
|
TZC_REGION_ACCESS_RDWR(FVP_NSAID_RES5));
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TODO: Interrupts are not currently supported. The only
|
||||||
|
* options we have are for access errors to occur quietly or to
|
||||||
|
* cause an exception. We choose to cause an exception.
|
||||||
|
*/
|
||||||
|
tzc_set_action(&controller, TZC_ACTION_ERR);
|
||||||
|
|
||||||
|
/* Enable filters. */
|
||||||
|
tzc_enable_filters(&controller);
|
||||||
|
}
|
|
@ -99,7 +99,8 @@
|
||||||
#define CONFIG_BASE_MMAP 7
|
#define CONFIG_BASE_MMAP 7
|
||||||
/* Indicates whether CCI should be enabled on the platform. */
|
/* Indicates whether CCI should be enabled on the platform. */
|
||||||
#define CONFIG_HAS_CCI 8
|
#define CONFIG_HAS_CCI 8
|
||||||
#define CONFIG_LIMIT 9
|
#define CONFIG_HAS_TZC 9
|
||||||
|
#define CONFIG_LIMIT 10
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* Platform memory map related constants
|
* Platform memory map related constants
|
||||||
|
@ -303,6 +304,28 @@
|
||||||
#define PL011_UART3_BASE 0x1c0c0000
|
#define PL011_UART3_BASE 0x1c0c0000
|
||||||
#define PL011_BASE PL011_UART0_BASE
|
#define PL011_BASE PL011_UART0_BASE
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* TrustZone address space controller related constants
|
||||||
|
******************************************************************************/
|
||||||
|
#define TZC400_BASE 0x2a4a0000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The NSAIDs for this platform as used to program the TZC400.
|
||||||
|
* TODO:
|
||||||
|
* This list and the numbers in it is still changing on the Base FVP.
|
||||||
|
* For now only specify the NSAIDs we actually use.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* The FVP has 4 bits of NSAIDs. Used with TZC FAIL_ID (ACE Lite ID width) */
|
||||||
|
#define FVP_AID_WIDTH 4
|
||||||
|
#define FVP_NSAID_DEFAULT 0
|
||||||
|
#define FVP_NSAID_AP 9 /* Application Processors */
|
||||||
|
|
||||||
|
/* FIXME: Currently incorrectly used by Virtio */
|
||||||
|
#define FVP_NSAID_RES5 15
|
||||||
|
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* Declarations and constants to access the mailboxes safely. Each mailbox is
|
* Declarations and constants to access the mailboxes safely. Each mailbox is
|
||||||
* aligned on the biggest cache line size in the platform. This is known only
|
* aligned on the biggest cache line size in the platform. This is known only
|
||||||
|
@ -374,6 +397,10 @@ extern void io_setup(void);
|
||||||
extern int plat_get_image_source(const char *image_name,
|
extern int plat_get_image_source(const char *image_name,
|
||||||
io_dev_handle *dev_handle, void **image_spec);
|
io_dev_handle *dev_handle, void **image_spec);
|
||||||
|
|
||||||
|
/* Declarations for plat_security.c */
|
||||||
|
extern void plat_security_setup(void);
|
||||||
|
|
||||||
|
|
||||||
#endif /*__ASSEMBLY__*/
|
#endif /*__ASSEMBLY__*/
|
||||||
|
|
||||||
#endif /* __PLATFORM_H__ */
|
#endif /* __PLATFORM_H__ */
|
||||||
|
|
|
@ -29,6 +29,7 @@
|
||||||
#
|
#
|
||||||
|
|
||||||
PLAT_INCLUDES := -Idrivers/arm/interconnect/cci-400 \
|
PLAT_INCLUDES := -Idrivers/arm/interconnect/cci-400 \
|
||||||
|
-Idrivers/arm/interconnect/tzc-400 \
|
||||||
-Idrivers/console \
|
-Idrivers/console \
|
||||||
-Idrivers/arm/peripherals/pl011 \
|
-Idrivers/arm/peripherals/pl011 \
|
||||||
-Idrivers/power
|
-Idrivers/power
|
||||||
|
@ -43,6 +44,7 @@ PLAT_BL1_C_VPATH := drivers/arm/interconnect/cci-400 \
|
||||||
PLAT_BL1_S_VPATH := lib/semihosting/${ARCH}
|
PLAT_BL1_S_VPATH := lib/semihosting/${ARCH}
|
||||||
|
|
||||||
PLAT_BL2_C_VPATH := drivers/arm/interconnect/cci-400 \
|
PLAT_BL2_C_VPATH := drivers/arm/interconnect/cci-400 \
|
||||||
|
drivers/arm/interconnect/tzc-400 \
|
||||||
drivers/arm/peripherals/pl011 \
|
drivers/arm/peripherals/pl011 \
|
||||||
lib/arch/${ARCH} \
|
lib/arch/${ARCH} \
|
||||||
lib/stdlib \
|
lib/stdlib \
|
||||||
|
@ -82,7 +84,9 @@ BL1_SOURCES += bl1_plat_setup.c \
|
||||||
|
|
||||||
BL2_SOURCES += bl2_plat_setup.c \
|
BL2_SOURCES += bl2_plat_setup.c \
|
||||||
platform_up_stack.S \
|
platform_up_stack.S \
|
||||||
plat_common.c
|
plat_common.c \
|
||||||
|
plat_security.c \
|
||||||
|
tzc400.c
|
||||||
|
|
||||||
BL31_SOURCES += bl31_plat_setup.c \
|
BL31_SOURCES += bl31_plat_setup.c \
|
||||||
plat_helpers.S \
|
plat_helpers.S \
|
||||||
|
|
Loading…
Reference in New Issue