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mediatek: mt8192: Add MPU support 

1 Add Domain1(PCIe device) protect address: 0x80000000~0x83FF0000.
2 Add Domain2(SSPM/SPM/DPM/MCUPM) protect address: 0x40000000~0x1FFFF0000.

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I4aaed37150076ae5943484c4adadac999a3d1762
This commit is contained in:
Xi Chen 2020-11-02 10:45:34 +08:00 committed by Yidi Lin
parent 29a8814f4e
commit 42f2fa823f
5 changed files with 232 additions and 0 deletions
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4
plat/mediatek/mt8192/bl31_plat_setup.c
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@ -16,6 +16,7 @@
#include <lib/coreboot.h>
/* Platform Includes */
#include <emi_mpu/emi_mpu.h>
#include <gpio/mtgpio.h>
#include <mt_gic_v3.h>
#include <mt_timer.h>
@ -89,6 +90,9 @@ void bl31_platform_setup(void)
ERROR("Failed to set default dcm on!!\n");
}
/* MPU Init */
emi_mpu_init();
/* Initialize the GIC driver, CPU and distributor interfaces */
mt_gic_driver_init();
mt_gic_init();

122
plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c Normal file
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@ -0,0 +1,122 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <emi_mpu.h>
#include <lib/mmio.h>
/*
* emi_mpu_set_region_protection: protect a region.
* @start: start address of the region
* @end: end address of the region
* @access_permission: EMI MPU access permission
* Return 0 for success, otherwise negative status code.
*/
static int _emi_mpu_set_protection(
unsigned long start, unsigned long end,
unsigned int apc)
{
unsigned int dgroup;
unsigned int region;
region = (start >> 24) & 0xFF;
start &= 0x00FFFFFF;
dgroup = (end >> 24) & 0xFF;
end &= 0x00FFFFFF;
if ((region >= EMI_MPU_REGION_NUM) || (dgroup > EMI_MPU_DGROUP_NUM)) {
WARN("Region:%u or dgroup:%u is wrong!\n", region, dgroup);
return -1;
}
apc &= 0x80FFFFFF;
if ((start >= DRAM_OFFSET) && (end >= start)) {
start -= DRAM_OFFSET;
end -= DRAM_OFFSET;
} else {
WARN("start:0x%lx or end:0x%lx address is wrong!\n",
start, end);
return -2;
}
mmio_write_32(EMI_MPU_SA(region), start);
mmio_write_32(EMI_MPU_EA(region), end);
mmio_write_32(EMI_MPU_APC(region, dgroup), apc);
return 0;
}
void dump_emi_mpu_regions(void)
{
unsigned long apc[EMI_MPU_DGROUP_NUM], sa, ea;
int region, i;
/* Only dump 8 regions(max: EMI_MPU_REGION_NUM --> 32) */
for (region = 0; region < 8; ++region) {
for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i)
apc[i] = mmio_read_32(EMI_MPU_APC(region, i));
sa = mmio_read_32(EMI_MPU_SA(region));
ea = mmio_read_32(EMI_MPU_EA(region));
WARN("region %d:\n", region);
WARN("\tsa:0x%lx, ea:0x%lx, apc0: 0x%lx apc1: 0x%lx\n",
sa, ea, apc[0], apc[1]);
}
}
int emi_mpu_set_protection(struct emi_region_info_t *region_info)
{
unsigned long start, end;
int i;
if (region_info->region >= EMI_MPU_REGION_NUM)
return -1;
start = (unsigned long)(region_info->start >> EMI_MPU_ALIGN_BITS) |
(region_info->region << 24);
for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) {
end = (unsigned long)(region_info->end >> EMI_MPU_ALIGN_BITS) |
(i << 24);
_emi_mpu_set_protection(start, end, region_info->apc[i]);
}
return 0;
}
void emi_mpu_init(void)
{
/* Set permission */
struct emi_region_info_t region_info;
/* PCE-e protect address(TODO) */
region_info.start = 0x80000000ULL;
region_info.end = 0x83FF0000ULL;
region_info.region = 1;
SET_ACCESS_PERMISSION(region_info.apc, 1,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, NO_PROT,
NO_PROT /*FORBIDDEN*/);
emi_mpu_set_protection(&region_info);
/* Forbidden All */
region_info.start = 0x40000000ULL; /* dram base addr */
region_info.end = 0x1FFFF0000ULL;
region_info.region = 2;
SET_ACCESS_PERMISSION(region_info.apc, 1,
NO_PROT, NO_PROT, NO_PROT, NO_PROT,
NO_PROT, NO_PROT, NO_PROT, NO_PROT,
NO_PROT, NO_PROT, NO_PROT, NO_PROT,
NO_PROT, FORBIDDEN, NO_PROT, NO_PROT);
emi_mpu_set_protection(&region_info);
dump_emi_mpu_regions();
}

102
plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.h Normal file
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@ -0,0 +1,102 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef EMI_MPU_H
#define EMI_MPU_H
#include <platform_def.h>
#define EMI_MPUP (EMI_BASE + 0x01D8)
#define EMI_MPUQ (EMI_BASE + 0x01E0)
#define EMI_MPUR (EMI_BASE + 0x01E8)
#define EMI_MPUS (EMI_BASE + 0x01F0)
#define EMI_MPUT (EMI_BASE + 0x01F8)
#define EMI_MPUY (EMI_BASE + 0x0220)
#define EMI_MPU_CTRL (EMI_MPU_BASE + 0x0000)
#define EMI_MPUD0_ST (EMI_BASE + 0x0160)
#define EMI_MPUD1_ST (EMI_BASE + 0x0164)
#define EMI_MPUD2_ST (EMI_BASE + 0x0168)
#define EMI_MPUD3_ST (EMI_BASE + 0x016C)
#define EMI_MPUD0_ST2 (EMI_BASE + 0x0200)
#define EMI_MPUD1_ST2 (EMI_BASE + 0x0204)
#define EMI_MPUD2_ST2 (EMI_BASE + 0x0208)
#define EMI_MPUD3_ST2 (EMI_BASE + 0x020C)
#define EMI_PHY_OFFSET (0x40000000UL)
#define NO_PROT (0)
#define SEC_RW (1)
#define SEC_RW_NSEC_R (2)
#define SEC_RW_NSEC_W (3)
#define SEC_R_NSEC_R (4)
#define FORBIDDEN (5)
#define SEC_R_NSEC_RW (6)
#define SECURE_OS_MPU_REGION_ID (0)
#define ATF_MPU_REGION_ID (1)
#define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
#define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region) * 4)
#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region) * 4)
#define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region) * 4 + \
(dgroup) * 0x100)
#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + domain * 4)
#define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900)
#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + domain * 4)
#define EMI_MPU_DOMAIN_NUM 16
#define EMI_MPU_REGION_NUM 32
#define EMI_MPU_ALIGN_BITS 16
#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS)
#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8)
#if (EMI_MPU_DGROUP_NUM == 1)
#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \
do { \
apc_ary[0] = 0; \
apc_ary[0] = \
(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) \
| (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) \
| (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) \
| (((unsigned int) d1) << 3) | ((unsigned int) d0) \
| (((unsigned int) lock) << 31); \
} while (0)
#elif (EMI_MPU_DGROUP_NUM == 2)
#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, \
d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \
do { \
apc_ary[1] = \
(((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) \
| (((unsigned int) d13) << 15) | (((unsigned int) d12) << 12) \
| (((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) \
| (((unsigned int) d9) << 3) | ((unsigned int) d8); \
apc_ary[0] = \
(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) \
| (((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) \
| (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) \
| (((unsigned int) d1) << 3) | ((unsigned int) d0) \
| (((unsigned int) lock) << 31); \
} while (0)
#endif
struct emi_region_info_t {
unsigned long long start;
unsigned long long end;
unsigned int region;
unsigned long apc[EMI_MPU_DGROUP_NUM];
};
void emi_mpu_init(void);
int emi_mpu_set_protection(struct emi_region_info_t *region_info);
void dump_emi_mpu_regions(void);
#endif /* __EMI_MPU_H */

2
plat/mediatek/mt8192/include/platform_def.h
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@ -30,6 +30,8 @@
#define GPIO_BASE (IO_PHYS + 0x00005000)
#define SPM_BASE (IO_PHYS + 0x00006000)
#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000)
#define EMI_BASE (IO_PHYS + 0x00219000)
#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000)
#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)

2
plat/mediatek/mt8192/platform.mk
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@ -11,6 +11,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT_SOC}/include/ \
-I${MTK_PLAT_SOC}/drivers/ \
-I${MTK_PLAT_SOC}/drivers/dcm \
-I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
@ -53,6 +54,7 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \