plat/hikey: boot memory layout to dedicated file
Boot memory layout is specific for a platform, but should not be mixed up with other platform specific attributes. A separate file is much cleaner and better to compare with other platforms. Take a look at plat/poplar where it is done the same way. Moved hikey_def.h to system include folder and moved includes from hikey_def.h to more general platform_def.h. Signed-off-by: Michael Brandl <git@fineon.pw>
This commit is contained in:
parent
16b05e94a2
commit
4368ae07ba
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@ -9,13 +9,12 @@
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <hikey_def.h>
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#include <hikey_layout.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <xlat_tables.h>
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#include "../hikey_def.h"
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#define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \
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DDR_SIZE - DDR_SEC_SIZE, \
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MT_DEVICE | MT_RW | MT_NS)
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@ -1,12 +1,12 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include "../hikey_def.h"
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#include <hikey_def.h>
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.globl plat_my_core_pos
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.globl platform_mem_init
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@ -13,14 +13,14 @@
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#include <emmc.h>
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#include <errno.h>
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#include <hi6220.h>
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#include <hikey_def.h>
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#include <hikey_layout.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <string.h>
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#include <tbbr/tbbr_img_desc.h>
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#include "../../bl1/bl1_private.h"
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#include "hikey_def.h"
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#include "hikey_private.h"
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/*
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@ -7,7 +7,7 @@
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#include <bl_common.h>
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#include <desc_image_load.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
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/*******************************************************************************
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@ -21,10 +21,9 @@
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#include <optee_utils.h>
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#endif
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#include <platform.h>
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#include <platform_def.h>
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#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
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#include <string.h>
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#include "hikey_def.h"
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#include "hikey_private.h"
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/*
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@ -14,12 +14,12 @@
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#include <errno.h>
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#include <gicv2.h>
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#include <hi6220.h>
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#include <hikey_def.h>
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#include <hisi_ipc.h>
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#include <hisi_pwrc.h>
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#include <mmio.h>
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#include <platform_def.h>
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#include "hikey_def.h"
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#include "hikey_private.h"
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/*
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <gicv2.h>
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#include <hi6220.h>
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#include <hikey_def.h>
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#include <hisi_ipc.h>
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#include <hisi_pwrc.h>
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#include <hisi_sram_map.h>
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@ -17,8 +18,6 @@
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#include <psci.h>
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#include <sp804_delay_timer.h>
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#include "hikey_def.h"
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#define CORE_PWR_STATE(state) \
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((state)->pwr_domain_state[MPIDR_AFFLVL0])
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#define CLUSTER_PWR_STATE(state) \
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __HIKEY_DEF_H__
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#define __HIKEY_DEF_H__
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#include <common_def.h>
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#include <tbbr_img_def.h>
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/* Always assume DDR is 1GB size. */
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#define DDR_BASE 0x0
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#define DDR_SIZE 0x40000000
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#define DEVICE_BASE 0xF4000000
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#define DEVICE_SIZE 0x05800000
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#define XG2RAM0_BASE 0xF9800000
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#define XG2RAM0_SIZE 0x00400000
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/* Memory location options for TSP */
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#define HIKEY_SRAM_ID 0
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#define HIKEY_DRAM_ID 1
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#define SRAM_BASE 0xFFF80000
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#define SRAM_SIZE 0x00012000
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/*
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* BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
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*/
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#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
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#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
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#define BL1_XG2RAM0_OFFSET 0x1000
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/*
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* PL011 related constants
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*/
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@ -0,0 +1,122 @@
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __HIKEY_LAYOUT_H
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#define __HIKEY_LAYOUT_H
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/*
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* Platform memory map related constants
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*/
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#define XG2RAM0_BASE 0xF9800000
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#define XG2RAM0_SIZE 0x00400000
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/*
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* BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
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*/
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#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
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#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
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#define BL1_XG2RAM0_OFFSET 0x1000
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/*
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* BL1 specific defines.
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*
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* Both loader and BL1_RO region stay in SRAM since they are used to simulate
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* ROM.
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* Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
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*
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* ++++++++++ 0xF980_0000
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* + loader +
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* ++++++++++ 0xF980_1000
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* + BL1_RO +
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* ++++++++++ 0xF981_0000
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* + BL1_RW +
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* ++++++++++ 0xF989_8000
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*/
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#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
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#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000)
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#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */
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#define BL1_RW_SIZE (0x00088000)
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#define BL1_RW_LIMIT (0xF9898000)
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/*
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* Non-Secure BL1U specific defines.
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*/
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#define NS_BL1U_BASE (0xf9818000)
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#define NS_BL1U_SIZE (0x00010000)
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#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
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/*
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* BL2 specific defines.
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*
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* Both loader and BL2 region stay in SRAM.
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* Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
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*
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* ++++++++++ 0xF980_0000
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* + loader +
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* ++++++++++ 0xF980_1000
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* + BL2 +
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* ++++++++++ 0xF981_8000
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*/
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#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
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#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */
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/*
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* SCP_BL2 specific defines.
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* In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
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* at 0x0100_0000. Then BL2 will parse the sections and loaded them into
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* predefined separated buffers.
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*/
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#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
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#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
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#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
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/*
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* BL31 specific defines.
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*/
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#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
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#define BL31_LIMIT (0xF9898000)
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/*
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* BL3-2 specific defines.
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*/
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/*
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* The TSP currently executes from TZC secured area of DRAM or SRAM.
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*/
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#define BL32_SRAM_BASE BL31_LIMIT
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#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
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#define BL32_DRAM_BASE DDR_SEC_BASE
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#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
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#ifdef SPD_opteed
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/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
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#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
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#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
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#endif
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#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
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#define BL32_BASE BL32_DRAM_BASE
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#define BL32_LIMIT BL32_DRAM_LIMIT
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#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
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#define BL32_BASE BL32_SRAM_BASE
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#define BL32_LIMIT BL32_SRAM_LIMIT
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#else
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#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
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#endif
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/* BL32 is mandatory in AArch32 */
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#ifndef AARCH32
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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#endif
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#endif /* !__HIKEY_LAYOUT_H */
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include "../hikey_def.h"
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#include <common_def.h>
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#include <hikey_def.h>
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#include <hikey_layout.h> /* BL memory region sizes, etc */
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#include <tbbr_img_def.h>
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_CORE_COUNT_PER_CLUSTER)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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PLATFORM_CLUSTER_COUNT + 1)
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#define PLAT_ARM_GICH_BASE 0xF6804000
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#define PLAT_ARM_GICV_BASE 0xF6806000
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/*
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* Platform memory map related constants
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*/
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/*
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* BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
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*/
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#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
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#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
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#define BL1_XG2RAM0_OFFSET 0x1000
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/*
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* BL1 specific defines.
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*
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* Both loader and BL1_RO region stay in SRAM since they are used to simulate
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* ROM.
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* Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
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*
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* ++++++++++ 0xF980_0000
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* + loader +
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* ++++++++++ 0xF980_1000
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* + BL1_RO +
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* ++++++++++ 0xF981_0000
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* + BL1_RW +
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* ++++++++++ 0xF989_8000
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*/
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#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
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#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000)
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#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */
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#define BL1_RW_SIZE (0x00088000)
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#define BL1_RW_LIMIT (0xF9898000)
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/*
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* BL2 specific defines.
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*
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* Both loader and BL2 region stay in SRAM.
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* Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
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*
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* ++++++++++ 0xF980_0000
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* + loader +
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* ++++++++++ 0xF980_1000
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* + BL2 +
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* ++++++++++ 0xF981_8000
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*/
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#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
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#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */
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/*
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* SCP_BL2 specific defines.
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* In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
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* at 0x0100_0000. Then BL2 will parse the sections and loaded them into
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* predefined separated buffers.
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*/
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#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
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#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
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#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
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/*
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* BL31 specific defines.
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*/
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#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
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#define BL31_LIMIT (0xF9898000)
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/*
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* BL3-2 specific defines.
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*/
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/*
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* The TSP currently executes from TZC secured area of DRAM or SRAM.
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*/
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#define BL32_SRAM_BASE BL31_LIMIT
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#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
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#define BL32_DRAM_BASE DDR_SEC_BASE
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#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
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#ifdef SPD_opteed
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/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
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#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
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#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
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#endif
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#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
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#define BL32_BASE BL32_DRAM_BASE
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#define BL32_LIMIT BL32_DRAM_LIMIT
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#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
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#define BL32_BASE BL32_SRAM_BASE
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#define BL32_LIMIT BL32_SRAM_LIMIT
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#else
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#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
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#endif
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/* BL32 is mandatory in AArch32 */
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#ifndef AARCH32
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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#endif
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#define NS_BL1U_BASE (0xf9818000)
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#define NS_BL1U_SIZE (0x00010000)
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#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
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/*
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* Platform specific page table and MMU setup constants
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*/
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#define MAX_MMAP_REGIONS 16
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#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
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/*
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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