Merge pull request #409 from sandrine-bailleux/sb/break-down-bl1-sync-exceptions
Break down BL1 AArch64 synchronous exception handler
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commit
4425448a01
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@ -115,51 +115,13 @@ SynchronousExceptionA64:
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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/* ------------------------------------------------
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* Only a single SMC exception from BL2 to ask
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* BL1 to pass EL3 control to BL31 is expected
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* here.
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* It expects X0 with RUN_IMAGE SMC function id
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* X1 with address of a entry_point_info_t structure
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* describing the BL3-1 entrypoint
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* ------------------------------------------------
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*/
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mov x19, x0
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mov x20, x1
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/* Expect only SMC exceptions */
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mrs x19, esr_el3
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ubfx x20, x19, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x20, #EC_AARCH64_SMC
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b.ne unexpected_sync_exception
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mrs x0, esr_el3
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ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x1, #EC_AARCH64_SMC
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b.ne panic
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mov x0, #RUN_IMAGE
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cmp x19, x0
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b.ne panic
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mov x0, x20
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bl display_boot_progress
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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ubfx x0, x1, #MODE_EL_SHIFT, #2
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cmp x0, #MODE_EL3
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b.ne panic
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bl disable_mmu_icache_el3
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tlbi alle3
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ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
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ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
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eret
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panic:
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mov x0, #SYNC_EXCEPTION_AARCH64
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bl plat_report_exception
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wfi
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b panic
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b smc_handler64
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check_vector_size SynchronousExceptionA64
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.align 7
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@ -214,3 +176,46 @@ SErrorA32:
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bl plat_report_exception
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b SErrorA32
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check_vector_size SErrorA32
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func smc_handler64
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/* ---------------------------------------------------------------------
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* Only a single SMC exception from BL2 to ask BL1 to pass EL3 control
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* to BL31 is expected here. It expects:
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* - X0 with RUN_IMAGE SMC function ID;
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* - X1 with the address of a entry_point_info_t structure describing
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* the BL31 entrypoint.
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* ---------------------------------------------------------------------
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*/
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mov x19, x0
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mov x20, x1
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mov x0, #RUN_IMAGE
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cmp x19, x0
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b.ne unexpected_sync_exception
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mov x0, x20
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bl display_boot_progress
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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ubfx x0, x1, #MODE_EL_SHIFT, #2
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cmp x0, #MODE_EL3
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b.ne unexpected_sync_exception
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bl disable_mmu_icache_el3
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tlbi alle3
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ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
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ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
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eret
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endfunc smc_handler64
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unexpected_sync_exception:
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mov x0, #SYNC_EXCEPTION_AARCH64
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bl plat_report_exception
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wfi
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b unexpected_sync_exception
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