plat/fvp: Add support for dynamic description of secure interrupts
Using the fconf framework, the Group 0 and Group 1 secure interrupt descriptors are moved to device tree and retrieved in runtime. This feature is enabled by the build flag SEC_INT_DESC_IN_FCONF. Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
This commit is contained in:
Madhukar Pappireddy
parent
16af48e4cd
commit
452d5e5ef1
2
Makefile
2
Makefile
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@ -889,6 +889,7 @@ $(eval $(call assert_boolean,USE_COHERENT_MEM))
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$(eval $(call assert_boolean,USE_DEBUGFS))
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$(eval $(call assert_boolean,ARM_IO_IN_DTB))
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$(eval $(call assert_boolean,SDEI_IN_FCONF))
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$(eval $(call assert_boolean,SEC_INT_DESC_IN_FCONF))
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$(eval $(call assert_boolean,USE_ROMLIB))
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$(eval $(call assert_boolean,USE_TBBR_DEFS))
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$(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY))
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@ -969,6 +970,7 @@ $(eval $(call add_define,USE_COHERENT_MEM))
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$(eval $(call add_define,USE_DEBUGFS))
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$(eval $(call add_define,ARM_IO_IN_DTB))
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$(eval $(call add_define,SDEI_IN_FCONF))
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$(eval $(call add_define,SEC_INT_DESC_IN_FCONF))
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$(eval $(call add_define,USE_ROMLIB))
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$(eval $(call add_define,USE_TBBR_DEFS))
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$(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY))
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@ -651,6 +651,12 @@ Common build options
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than static C structures at compile time. This is currently an experimental
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feature and is only supported if SDEI_SUPPORT build flag is enabled.
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- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0
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and Group1 secure interrupts using the firmware configuration framework. The
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platform specific secure interrupt property descriptor is retrieved from
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device tree in runtime rather than depending on static C structure at compile
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time. This is currently an experimental feature.
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- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
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This feature creates a library of functions to be placed in ROM and thus
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reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default
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@ -6,6 +6,11 @@
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#include <services/sdei_flags.h>
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#define LEVEL 0
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#define EDGE 2
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#define SDEI_NORMAL 0x70
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#define HIGHEST_SEC 0
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/memreserve/ 0x80000000 0x00010000;
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/ {
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@ -38,8 +43,9 @@
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max-pwr-lvl = <2>;
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};
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#if SDEI_IN_FCONF
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#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF
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firmware {
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#if SDEI_IN_FCONF
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sdei {
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compatible = "arm,sdei-1.0";
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method = "smc";
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@ -59,9 +65,38 @@
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<2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
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<2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
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};
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};
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#endif /* SDEI_IN_FCONF */
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#if SEC_INT_DESC_IN_FCONF
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sec_interrupts {
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compatible = "arm,secure_interrupt_desc";
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/* Number of G0 and G1 secure interrupts defined by the platform */
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g0_intr_cnt = <2>;
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g1s_intr_cnt = <9>;
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. Each interrupt property descriptor has 3 fields:
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* 1. Interrupt number
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* 2. Interrupt priority
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* 3. Type of interrupt (Edge or Level configured)
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*/
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g0_intr_desc = < 8 SDEI_NORMAL EDGE>,
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<14 HIGHEST_SEC EDGE>;
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g1s_intr_desc = < 9 HIGHEST_SEC EDGE>,
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<10 HIGHEST_SEC EDGE>,
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<11 HIGHEST_SEC EDGE>,
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<12 HIGHEST_SEC EDGE>,
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<13 HIGHEST_SEC EDGE>,
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<15 HIGHEST_SEC EDGE>,
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<29 HIGHEST_SEC LEVEL>,
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<56 HIGHEST_SEC LEVEL>,
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<57 HIGHEST_SEC LEVEL>;
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};
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#endif /* SEC_INT_DESC_IN_FCONF */
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};
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#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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@ -0,0 +1,27 @@
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FCONF_SEC_INTR_CONFIG_H
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#define FCONF_SEC_INTR_CONFIG_H
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#include <lib/fconf/fconf.h>
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#include <platform_def.h>
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#define hw_config__sec_intr_prop_getter(id) sec_intr_prop.id
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#define SEC_INT_COUNT_MAX U(15)
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struct sec_intr_prop_t {
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interrupt_prop_t descriptor[SEC_INT_COUNT_MAX];
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uint32_t count;
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};
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int fconf_populate_sec_intr_config(uintptr_t config);
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extern struct sec_intr_prop_t sec_intr_prop;
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#endif /* FCONF_SEC_INTR_CONFIG_H */
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@ -226,7 +226,10 @@ USE_DEBUGFS := 0
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ARM_IO_IN_DTB := 0
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# Build option to support SDEI through fconf
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SDEI_IN_FCONF :=0
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SDEI_IN_FCONF := 0
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# Build option to support Secure Interrupt descriptors through fconf
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SEC_INT_DESC_IN_FCONF := 0
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# Build option to choose whether Trusted Firmware uses library at ROM
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USE_ROMLIB := 0
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@ -12,6 +12,7 @@
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#include <fconf_hw_config_getter.h>
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#include <lib/utils.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/arm/common/fconf_sec_intr_config.h>
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#include <plat/common/platform.h>
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/* The GICv3 driver only needs to be initialized in EL3 */
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@ -23,10 +24,13 @@ static uint64_t fvp_gicr_base_addrs[2] = { 0U };
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/* List of zero terminated GICR frame addresses which CPUs will probe */
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static uint64_t *fvp_gicr_frames = fvp_gicr_base_addrs;
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#if !(SEC_INT_DESC_IN_FCONF && ((!defined(__aarch64__) && defined(IMAGE_BL32)) || \
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(defined(__aarch64__) && defined(IMAGE_BL31))))
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static const interrupt_prop_t fvp_interrupt_props[] = {
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PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
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PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
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};
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#endif
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/*
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* MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
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@ -52,8 +56,6 @@ static unsigned int fvp_gicv3_mpidr_hash(u_register_t mpidr)
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static gicv3_driver_data_t fvp_gic_data = {
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.interrupt_props = fvp_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = fvp_rdistif_base_addrs,
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.mpidr_to_core_pos = fvp_gicv3_mpidr_hash
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@ -61,7 +63,10 @@ static gicv3_driver_data_t fvp_gic_data = {
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void plat_arm_gic_driver_init(void)
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{
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/* Get GICD and GICR base addressed through FCONF APIs */
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/*
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* Get GICD and GICR base addressed through FCONF APIs.
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* FCONF is not supported in BL32 for FVP.
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*/
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#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
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(defined(__aarch64__) && defined(IMAGE_BL31))
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fvp_gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config,
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@ -69,9 +74,20 @@ void plat_arm_gic_driver_init(void)
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gicd_base);
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fvp_gicr_base_addrs[0] = FCONF_GET_PROPERTY(hw_config, gicv3_config,
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gicr_base);
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#if SEC_INT_DESC_IN_FCONF
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fvp_gic_data.interrupt_props = FCONF_GET_PROPERTY(hw_config,
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sec_intr_prop, descriptor);
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fvp_gic_data.interrupt_props_num = FCONF_GET_PROPERTY(hw_config,
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sec_intr_prop, count);
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#else
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fvp_gic_data.interrupt_props = fvp_interrupt_props;
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fvp_gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
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#endif
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#else
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fvp_gic_data.gicd_base = PLAT_ARM_GICD_BASE;
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fvp_gicr_base_addrs[0] = PLAT_ARM_GICR_BASE;
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fvp_gic_data.interrupt_props = fvp_interrupt_props;
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fvp_gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
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#endif
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/*
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@ -221,6 +221,11 @@ ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_BL31}),)
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BL31_SOURCES += common/fdt_wrappers.c \
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lib/fconf/fconf.c \
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plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
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ifeq (${SEC_INT_DESC_IN_FCONF},1)
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BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c
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endif
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endif
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ifeq (${FVP_USE_SP804_TIMER},1)
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@ -25,6 +25,11 @@ ifeq ($(filter 1,${BL2_AT_EL3} ${RESET_TO_SP_MIN}),)
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BL32_SOURCES += common/fdt_wrappers.c \
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lib/fconf/fconf.c \
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plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
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ifeq (${SEC_INT_DESC_IN_FCONF},1)
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BL32_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c
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endif
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endif
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include plat/arm/common/sp_min/arm_sp_min.mk
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@ -0,0 +1,131 @@
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/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <common/fdt_wrappers.h>
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#include <libfdt.h>
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#include <plat/arm/common/fconf_sec_intr_config.h>
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#define G0_INTR_NUM(i) g0_intr_prop[3U * (i)]
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#define G0_INTR_PRIORITY(i) g0_intr_prop[3U * (i) + 1]
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#define G0_INTR_CONFIG(i) g0_intr_prop[3U * (i) + 2]
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#define G1S_INTR_NUM(i) g1s_intr_prop[3U * (i)]
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#define G1S_INTR_PRIORITY(i) g1s_intr_prop[3U * (i) + 1]
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#define G1S_INTR_CONFIG(i) g1s_intr_prop[3U * (i) + 2]
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struct sec_intr_prop_t sec_intr_prop;
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static void print_intr_prop(interrupt_prop_t prop)
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{
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VERBOSE("FCONF: Secure Interrupt NUM: %d, PRI: %d, TYPE: %d\n",
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prop.intr_num, prop.intr_pri, prop.intr_cfg);
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}
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int fconf_populate_sec_intr_config(uintptr_t config)
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{
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int node, err;
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uint32_t g0_intr_count, g1s_intr_count;
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uint32_t g0_intr_prop[SEC_INT_COUNT_MAX * 3];
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uint32_t g1s_intr_prop[SEC_INT_COUNT_MAX * 3];
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/* Necessary to work with libfdt APIs */
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const void *hw_config_dtb = (const void *)config;
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node = fdt_node_offset_by_compatible(hw_config_dtb, -1,
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"arm,secure_interrupt_desc");
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if (node < 0) {
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ERROR("FCONF: Unable to locate node with %s compatible property\n",
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"arm,secure_interrupt_desc");
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return node;
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}
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/* Read number of Group 0 interrupts specified by platform */
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err = fdt_read_uint32(hw_config_dtb, node, "g0_intr_cnt", &g0_intr_count);
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if (err < 0) {
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ERROR("FCONF: Could not locate g0s_intr_cnt property\n");
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return err;
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}
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/* At least 1 Group 0 interrupt description has to be provided*/
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if (g0_intr_count < 1U) {
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ERROR("FCONF: Invalid number of Group 0 interrupts count specified\n");
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return -1;
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}
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/* Read number of Group 1 secure interrupts specified by platform */
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err = fdt_read_uint32(hw_config_dtb, node, "g1s_intr_cnt",
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&g1s_intr_count);
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if (err < 0) {
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ERROR("FCONF: Could not locate g1s_intr_cnt property\n");
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return err;
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}
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/* At least one Group 1 interrupt description has to be provided*/
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if (g1s_intr_count < 1U) {
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ERROR("FCONF: Invalid number of Group 1 secure interrupts count specified\n");
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return -1;
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}
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/*
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* Check if the total number of secure interrupts described are within
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* the limit defined statically by the platform.
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*/
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if ((g0_intr_count + g1s_intr_count) > SEC_INT_COUNT_MAX) {
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ERROR("FCONF: Total number of secure interrupts exceed limit the of %d\n",
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SEC_INT_COUNT_MAX);
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return -1;
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}
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sec_intr_prop.count = g0_intr_count + g1s_intr_count;
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/* Read the Group 0 interrupt descriptors */
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err = fdt_read_uint32_array(hw_config_dtb, node, "g0_intr_desc",
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g0_intr_count * 3, g0_intr_prop);
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if (err < 0) {
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ERROR("FCONF: Read cell failed for 'g0s_intr_desc': %d\n", err);
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return err;
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}
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/* Read the Group 1 secure interrupt descriptors */
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err = fdt_read_uint32_array(hw_config_dtb, node, "g1s_intr_desc",
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g1s_intr_count * 3, g1s_intr_prop);
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if (err < 0) {
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ERROR("FCONF: Read cell failed for 'g1s_intr_desc': %d\n", err);
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return err;
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}
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/* Populate Group 0 interrupt descriptors into fconf based C struct */
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for (uint32_t i = 0; i < g0_intr_count; i++) {
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interrupt_prop_t sec_intr_property;
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/* Secure Interrupt Group: INTR_GROUP0 i.e., 0x1 */
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sec_intr_property.intr_grp = 1;
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sec_intr_property.intr_num = G0_INTR_NUM(i);
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sec_intr_property.intr_pri = G0_INTR_PRIORITY(i);
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sec_intr_property.intr_cfg = G0_INTR_CONFIG(i);
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sec_intr_prop.descriptor[i] = sec_intr_property;
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print_intr_prop(sec_intr_property);
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}
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/* Populate G1 secure interrupt descriptors into fconf based C struct */
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for (uint32_t i = 0; i < g1s_intr_count; i++) {
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interrupt_prop_t sec_intr_property;
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/* Secure Interrupt Group: INTR_GROUP1S i.e., 0x0 */
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sec_intr_property.intr_grp = 0;
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sec_intr_property.intr_num = G1S_INTR_NUM(i);
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sec_intr_property.intr_pri = G1S_INTR_PRIORITY(i);
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sec_intr_property.intr_cfg = G1S_INTR_CONFIG(i);
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sec_intr_prop.descriptor[i + g0_intr_count] = sec_intr_property;
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print_intr_prop(sec_intr_property);
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}
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return 0;
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}
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FCONF_REGISTER_POPULATOR(HW_CONFIG, sec_intr_prop, fconf_populate_sec_intr_config);
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