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drivers: stm32_reset adapt interface to timeout argument 

Changes stm32mp1 reset driver to API to add a timeout argument
to stm32mp_reset_assert() and stm32mp_reset_deassert() and
a return value.

With a supplied timeout, the functions wait the target reset state
is reached before returning. With a timeout of zero, the functions
simply load target reset state in SoC interface and return without
waiting.

Helper functions stm32mp_reset_set() and stm32mp_reset_release()
use a zero timeout and return without a return code.

This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c
accordingly without any functional change.
functional change.

Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This commit is contained in:
Etienne Carriere 2019-12-08 08:14:40 +01:00 committed by Etienne Carriere
parent 4e2887f2da
commit 45c70e6867
7 changed files with 114 additions and 26 deletions
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11
drivers/st/crypto/stm32_hash.c
View File

@ -51,6 +51,7 @@
#define SHA224_DIGEST_SIZE 28U
#define SHA256_DIGEST_SIZE 32U
#define RESET_TIMEOUT_US_1MS 1000U
#define HASH_TIMEOUT_US 10000U
enum stm32_hash_data_format {
@ -319,9 +320,15 @@ int stm32_hash_register(void)
stm32mp_clk_enable(stm32_hash.clock);
if (hash_info.reset >= 0) {
stm32mp_reset_assert((unsigned long)hash_info.reset);
uint32_t id = (uint32_t)hash_info.reset;
if (stm32mp_reset_assert(id, RESET_TIMEOUT_US_1MS) != 0) {
panic();
}
udelay(20);
stm32mp_reset_deassert((unsigned long)hash_info.reset);
if (stm32mp_reset_deassert(id, RESET_TIMEOUT_US_1MS) != 0) {
panic();
}
}
stm32mp_clk_disable(stm32_hash.clock);

14
drivers/st/fmc/stm32_fmc2_nand.c
View File

@ -22,6 +22,9 @@
#include <lib/mmio.h>
#include <lib/utils_def.h>
/* Timeout for device interface reset */
#define TIMEOUT_US_1_MS 1000U
/* FMC2 Compatibility */
#define DT_FMC2_COMPAT "st,stm32mp15-fmc2"
#define MAX_CS 2U
@ -793,6 +796,7 @@ int stm32_fmc2_init(void)
void *fdt = NULL;
const fdt32_t *cuint;
struct dt_node_info info;
int ret;
if (fdt_get_address(&fdt) == 0) {
return -FDT_ERR_NOTFOUND;
@ -861,8 +865,14 @@ int stm32_fmc2_init(void)
stm32mp_clk_enable(stm32_fmc2.clock_id);
/* Reset IP */
stm32mp_reset_assert(stm32_fmc2.reset_id);
stm32mp_reset_deassert(stm32_fmc2.reset_id);
ret = stm32mp_reset_assert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS);
if (ret != 0) {
panic();
}
ret = stm32mp_reset_deassert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS);
if (ret != 0) {
panic();
}
/* Setup default IP registers */
stm32_fmc2_ctrl_init();

13
drivers/st/mmc/stm32_sdmmc2.c
View File

@ -113,6 +113,7 @@
SDMMC_STAR_IDMATE | \
SDMMC_STAR_IDMABTC)
#define TIMEOUT_US_1_MS 1000U
#define TIMEOUT_US_10_MS 10000U
#define TIMEOUT_US_1_S 1000000U
@ -711,6 +712,8 @@ unsigned long long stm32_sdmmc2_mmc_get_device_size(void)
int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
{
int rc;
assert((params != NULL) &&
((params->reg_base & MMC_BLOCK_MASK) == 0U) &&
((params->bus_width == MMC_BUS_WIDTH_1) ||
@ -726,9 +729,15 @@ int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
stm32mp_clk_enable(sdmmc2_params.clock_id);
stm32mp_reset_assert(sdmmc2_params.reset_id);
rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS);
if (rc != 0) {
panic();
}
udelay(2);
stm32mp_reset_deassert(sdmmc2_params.reset_id);
rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS);
if (rc != 0) {
panic();
}
mdelay(1);
sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id);

35
drivers/st/reset/stm32mp1_reset.c
View File

@ -4,6 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
#include <limits.h>
#include <platform_def.h>
@ -15,8 +16,6 @@
#include <lib/mmio.h>
#include <lib/utils_def.h>
#define RESET_TIMEOUT_US_1MS U(1000)
static uint32_t id2reg_offset(unsigned int reset_id)
{
return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t);
@ -27,36 +26,44 @@ static uint8_t id2reg_bit_pos(unsigned int reset_id)
return (uint8_t)(reset_id & GENMASK(4, 0));
}
void stm32mp_reset_assert(uint32_t id)
int stm32mp_reset_assert(uint32_t id, unsigned int to_us)
{
uint32_t offset = id2reg_offset(id);
uint32_t bitmsk = BIT(id2reg_bit_pos(id));
uint64_t timeout_ref;
uintptr_t rcc_base = stm32mp_rcc_base();
mmio_write_32(rcc_base + offset, bitmsk);
timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS);
while ((mmio_read_32(rcc_base + offset) & bitmsk) == 0U) {
if (timeout_elapsed(timeout_ref)) {
panic();
if (to_us != 0U) {
uint64_t timeout_ref = timeout_init_us(to_us);
while ((mmio_read_32(rcc_base + offset) & bitmsk) == 0U) {
if (timeout_elapsed(timeout_ref)) {
return -ETIMEDOUT;
}
}
}
return 0;
}
void stm32mp_reset_deassert(uint32_t id)
int stm32mp_reset_deassert(uint32_t id, unsigned int to_us)
{
uint32_t offset = id2reg_offset(id) + RCC_RSTCLRR_OFFSET;
uint32_t bitmsk = BIT(id2reg_bit_pos(id));
uint64_t timeout_ref;
uintptr_t rcc_base = stm32mp_rcc_base();
mmio_write_32(rcc_base + offset, bitmsk);
timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS);
while ((mmio_read_32(rcc_base + offset) & bitmsk) != 0U) {
if (timeout_elapsed(timeout_ref)) {
panic();
if (to_us != 0U) {
uint64_t timeout_ref = timeout_init_us(to_us);
while ((mmio_read_32(rcc_base + offset) & bitmsk) != 0U) {
if (timeout_elapsed(timeout_ref)) {
return -ETIMEDOUT;
}
}
}
return 0;
}

13
drivers/st/spi/stm32_qspi.c
View File

@ -18,6 +18,9 @@
#include <lib/mmio.h>
#include <lib/utils_def.h>
/* Timeout for device interface reset */
#define TIMEOUT_US_1_MS 1000U
/* QUADSPI registers */
#define QSPI_CR 0x00U
#define QSPI_DCR 0x04U
@ -492,8 +495,14 @@ int stm32_qspi_init(void)
stm32mp_clk_enable(stm32_qspi.clock_id);
stm32mp_reset_assert(stm32_qspi.reset_id);
stm32mp_reset_deassert(stm32_qspi.reset_id);
ret = stm32mp_reset_assert(stm32_qspi.reset_id, TIMEOUT_US_1_MS);
if (ret != 0) {
panic();
}
ret = stm32mp_reset_deassert(stm32_qspi.reset_id, TIMEOUT_US_1_MS);
if (ret != 0) {
panic();
}
mmio_write_32(qspi_base() + QSPI_CR, QSPI_CR_SSHIFT);
mmio_write_32(qspi_base() + QSPI_DCR, QSPI_DCR_FSIZE_MASK);

39
include/drivers/st/stm32mp_reset.h
View File

@ -9,7 +9,42 @@
#include <stdint.h>
void stm32mp_reset_assert(uint32_t reset_id);
void stm32mp_reset_deassert(uint32_t reset_id);
/*
* Assert target reset, if @to_us non null, wait until reset is asserted
*
* @reset_id: Reset controller ID
* @to_us: Timeout in microsecond, or 0 if not waiting
* Return 0 on success and -ETIMEDOUT if waiting and timeout expired
*/
int stm32mp_reset_assert(uint32_t reset_id, unsigned int to_us);
/*
* Enable reset control for target resource
*
* @reset_id: Reset controller ID
*/
static inline void stm32mp_reset_set(uint32_t reset_id)
{
(void)stm32mp_reset_assert(reset_id, 0U);
}
/*
* Deassert target reset, if @to_us non null, wait until reset is deasserted
*
* @reset_id: Reset controller ID
* @to_us: Timeout in microsecond, or 0 if not waiting
* Return 0 on success and -ETIMEDOUT if waiting and timeout expired
*/
int stm32mp_reset_deassert(uint32_t reset_id, unsigned int to_us);
/*
* Release reset control for target resource
*
* @reset_id: Reset controller ID
*/
static inline void stm32mp_reset_release(uint32_t reset_id)
{
(void)stm32mp_reset_deassert(reset_id, 0U);
}
#endif /* STM32MP_RESET_H */

15
plat/st/stm32mp1/bl2_plat_setup.c
View File

@ -31,6 +31,8 @@
#include <stm32mp1_context.h>
#include <stm32mp1_dbgmcu.h>
#define RESET_TIMEOUT_US_1MS 1000U
static console_t console;
static struct stm32mp_auth_ops stm32mp1_auth_ops;
@ -263,9 +265,18 @@ void bl2_el3_plat_arch_setup(void)
stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
stm32mp_reset_assert((uint32_t)dt_uart_info.reset);
if (stm32mp_reset_assert((uint32_t)dt_uart_info.reset,
RESET_TIMEOUT_US_1MS) != 0) {
panic();
}
udelay(2);
stm32mp_reset_deassert((uint32_t)dt_uart_info.reset);
if (stm32mp_reset_deassert((uint32_t)dt_uart_info.reset,
RESET_TIMEOUT_US_1MS) != 0) {
panic();
}
mdelay(1);
clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);