fconf: Extract topology node properties from HW_CONFIG dtb
Create, register( and implicitly invoke) fconf_populate_topology() function which extracts the topology related properties from dtb into the newly created fconf based configuration structure 'soc_topology'. Appropriate libfdt APIs are added to jmptbl.i file for use with USE_ROMLIB build feature. A new property which describes the power domain levels is added to the HW_CONFIG device tree source files. This patch also fixes a minor bug in the common device tree file fvp-base-gicv3-psci-dynamiq-common.dtsi As this file includes fvp-base-gicv3-psci-common.dtsi, it is necessary to delete all previous cluster node definitons because DynamIQ based models have upto 8 CPUs in each cluster. If not deleted, the final dts would have an inaccurate description of SoC topology, i.e., cluster0 with 8 or more core nodes and cluster1 with 4 core nodes. Change-Id: I9eb406da3ba4732008a66c01afec7c9fa8ef59bf Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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26d1e0c330
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@ -35,6 +35,7 @@
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cpu_on = <0x84000003>;
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cpu_on = <0x84000003>;
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sys_poweroff = <0x84000008>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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sys_reset = <0x84000009>;
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max-pwr-lvl = <2>;
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};
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};
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cpus {
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cpus {
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@ -35,6 +35,7 @@
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cpu_on = <0xc4000003>;
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cpu_on = <0xc4000003>;
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sys_poweroff = <0x84000008>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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sys_reset = <0x84000009>;
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max-pwr-lvl = <2>;
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};
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};
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cpus {
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cpus {
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@ -33,6 +33,7 @@
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cpu_on = <0x84000003>;
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cpu_on = <0x84000003>;
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sys_poweroff = <0x84000008>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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sys_reset = <0x84000009>;
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max-pwr-lvl = <2>;
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};
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};
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cpus {
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cpus {
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@ -33,6 +33,7 @@
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cpu_on = <0xc4000003>;
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cpu_on = <0xc4000003>;
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sys_poweroff = <0x84000008>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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sys_reset = <0x84000009>;
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max-pwr-lvl = <2>;
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};
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};
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cpus {
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cpus {
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@ -11,6 +11,9 @@
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/* DynamIQ based designs have upto 8 CPUs in each cluster */
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/* DynamIQ based designs have upto 8 CPUs in each cluster */
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&CPU_MAP {
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&CPU_MAP {
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/delete-node/ cluster0;
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/delete-node/ cluster1;
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cluster0 {
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cluster0 {
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core0 {
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core0 {
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cpu = <&CPU0>;
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cpu = <&CPU0>;
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@ -35,6 +35,7 @@
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cpu_on = <0xc4000003>;
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cpu_on = <0xc4000003>;
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sys_poweroff = <0x84000008>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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sys_reset = <0x84000009>;
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max-pwr-lvl = <2>;
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};
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};
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cpus {
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cpus {
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@ -35,6 +35,7 @@
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cpu_on = <0xc4000003>;
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cpu_on = <0xc4000003>;
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sys_poweroff = <0x84000008>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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sys_reset = <0x84000009>;
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max-pwr-lvl = <2>;
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};
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};
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cpus {
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cpus {
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@ -12,6 +12,7 @@
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#include <plat/common/platform.h>
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#include <plat/common/platform.h>
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struct gicv3_config_t gicv3_config;
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struct gicv3_config_t gicv3_config;
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struct hw_topology_t soc_topology;
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int fconf_populate_gicv3_config(uintptr_t config)
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int fconf_populate_gicv3_config(uintptr_t config)
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{
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{
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@ -48,5 +49,120 @@ int fconf_populate_gicv3_config(uintptr_t config)
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return err;
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return err;
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}
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}
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int fconf_populate_topology(uintptr_t config)
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{
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int err, node, cluster_node, core_node, thread_node, max_pwr_lvl = 0;
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uint32_t cluster_count = 0, max_cpu_per_cluster = 0, total_cpu_count = 0;
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/* Necessary to work with libfdt APIs */
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const void *hw_config_dtb = (const void *)config;
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/* Find the offset of the node containing "arm,psci-1.0" compatible property */
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node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,psci-1.0");
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if (node < 0) {
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ERROR("FCONF: Unable to locate node with arm,psci-1.0 compatible property\n");
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return node;
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}
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err = fdtw_read_cells(hw_config_dtb, node, "max-pwr-lvl", 1, &max_pwr_lvl);
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if (err < 0) {
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/*
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* Some legacy FVP dts may not have this property. Assign the default
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* value.
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*/
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WARN("FCONF: Could not locate max-pwr-lvl property\n");
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max_pwr_lvl = 2;
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}
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assert((uint32_t)max_pwr_lvl <= MPIDR_AFFLVL2);
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/* Find the offset of the "cpus" node */
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node = fdt_path_offset(hw_config_dtb, "/cpus");
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if (node < 0) {
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ERROR("FCONF: Node '%s' not found in hardware configuration dtb\n", "cpus");
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return node;
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}
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/* A typical cpu-map node in a device tree is shown here for reference
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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};
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};
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*/
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/* Locate the cpu-map child node */
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node = fdt_subnode_offset(hw_config_dtb, node, "cpu-map");
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if (node < 0) {
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ERROR("FCONF: Node '%s' not found in hardware configuration dtb\n", "cpu-map");
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return node;
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}
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uint32_t cpus_per_cluster[PLAT_ARM_CLUSTER_COUNT] = {0};
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/* Iterate through cluster nodes */
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fdt_for_each_subnode(cluster_node, hw_config_dtb, node) {
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assert(cluster_count < PLAT_ARM_CLUSTER_COUNT);
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/* Iterate through core nodes */
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fdt_for_each_subnode(core_node, hw_config_dtb, cluster_node) {
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/* core nodes may have child nodes i.e., "thread" nodes */
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if (fdt_first_subnode(hw_config_dtb, core_node) < 0) {
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cpus_per_cluster[cluster_count]++;
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} else {
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/* Multi-threaded CPU description is found in dtb */
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fdt_for_each_subnode(thread_node, hw_config_dtb, core_node) {
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cpus_per_cluster[cluster_count]++;
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}
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/* Since in some dtbs, core nodes may not have thread node,
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* no need to error if even one child node is not found.
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*/
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}
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}
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/* Ensure every cluster node has at least 1 child node */
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if (cpus_per_cluster[cluster_count] < 1U) {
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ERROR("FCONF: Unable to locate the core node in cluster %d\n", cluster_count);
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return -1;
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}
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INFO("CLUSTER ID: %d cpu-count: %d\n", cluster_count, cpus_per_cluster[cluster_count]);
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/* Find the maximum number of cpus in any cluster */
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max_cpu_per_cluster = MAX(max_cpu_per_cluster, cpus_per_cluster[cluster_count]);
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total_cpu_count += cpus_per_cluster[cluster_count];
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cluster_count++;
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}
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/* At least one cluster node is expected in hardware configuration dtb */
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if (cluster_count < 1U) {
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ERROR("FCONF: Unable to locate the cluster node in cpu-map node\n");
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return -1;
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}
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soc_topology.plat_max_pwr_level = (uint32_t)max_pwr_lvl;
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soc_topology.plat_cluster_count = cluster_count;
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soc_topology.cluster_cpu_count = max_cpu_per_cluster;
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soc_topology.plat_cpu_count = total_cpu_count;
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return 0;
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}
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FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
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FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
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FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
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/* Hardware Config related getter */
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/* Hardware Config related getter */
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#define hw_config__gicv3_config_getter(prop) gicv3_config.prop
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#define hw_config__gicv3_config_getter(prop) gicv3_config.prop
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#define hw_config__topology_getter(prop) soc_topology.prop
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struct gicv3_config_t {
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struct gicv3_config_t {
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void *gicd_base;
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void *gicd_base;
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void *gicr_base;
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void *gicr_base;
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};
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};
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struct hw_topology_t {
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uint32_t plat_cluster_count;
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uint32_t cluster_cpu_count;
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uint32_t plat_cpu_count;
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uint32_t plat_max_pwr_level;
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};
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int fconf_populate_gicv3_config(uintptr_t config);
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int fconf_populate_gicv3_config(uintptr_t config);
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int fconf_populate_topology(uintptr_t config);
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extern struct gicv3_config_t gicv3_config;
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extern struct gicv3_config_t gicv3_config;
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extern struct hw_topology_t soc_topology;
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#endif /* FCONF_HW_CONFIG_GETTER_H */
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#endif /* FCONF_HW_CONFIG_GETTER_H */
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fdt fdt_setprop_inplace_namelen_partial
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fdt fdt_setprop_inplace_namelen_partial
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fdt fdt_first_subnode
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fdt fdt_first_subnode
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fdt fdt_next_subnode
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fdt fdt_next_subnode
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fdt fdt_path_offset
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fdt fdt_subnode_offset
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mbedtls mbedtls_asn1_get_alg
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mbedtls mbedtls_asn1_get_alg
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mbedtls mbedtls_asn1_get_alg_null
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mbedtls mbedtls_asn1_get_alg_null
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mbedtls mbedtls_asn1_get_bitstring_null
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mbedtls mbedtls_asn1_get_bitstring_null
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