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Tegra194: psci: rename 'percpu_data' variable 

The per CPU wake times are saved in an array called 't19x_percpu_data'. But,
there is one instance in the code where the name of the variable is misspelt.

This patch fixes this typographical error to fix compilation errors.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735
This commit is contained in:
Varun Wadekar 2019-12-03 08:50:57 -08:00
parent 2bcaeab663
commit 4719bba93d
1 changed files with 5 additions and 5 deletions
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10
plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
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@ -66,10 +66,10 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state,
<< TEGRA194_WAKE_TIME_SHIFT;
/*
* Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that
* the correct value is read in tegra_soc_pwr_domain_suspend(), which
* is called with caches disabled. It is possible to read a stale value
* from DRAM in that function, because the L2 cache is not flushed
* Clean t19x_percpu_data[cpu] to DRAM. This needs to be done to ensure
* that the correct value is read in tegra_soc_pwr_domain_suspend(),
* which is called with caches disabled. It is possible to read a stale
* value from DRAM in that function, because the L2 cache is not flushed
* unless the cluster is entering CC6/CC7.
*/
clean_dcache_range((uint64_t)&t19x_percpu_data[cpu],
@ -125,7 +125,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
(uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7;
ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
percpu_data[cpu].wake_time, 0);
t19x_percpu_data[cpu].wake_time, 0);
assert(ret == 0);
} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {