juno: Improve TZC-400 initialisation code
- Distinguish Juno specific from platform agnostic constants - Define constants for Juno TZC-400 NSAID
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@ -34,6 +34,7 @@
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#include <bl1.h>
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#include <console.h>
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#include <cci400.h>
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#include <tzc400.h>
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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@ -150,14 +151,6 @@ static void init_nic400(void)
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}
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#define TZC400_GATE_KEEPER_REG 0x008
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#define TZC400_REGION_ATTRIBUTES_0_REG 0x110
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#define TZC400_REGION_ID_ACCESS_0_REG 0x114
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#define TZC400_NSAID_WR_EN (1 << 16)
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#define TZC400_NSAID_RD_EN (1 << 0)
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#define TZC400_NSAID_RD_RW (TZC400_NSAID_WR_EN | TZC400_NSAID_RD_EN)
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static void init_tzc400(void)
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{
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/* Enable all filter units available */
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@ -174,17 +167,17 @@ static void init_tzc400(void)
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* Non-Secure World
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*/
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mmio_write_32(TZC400_BASE + TZC400_REGION_ID_ACCESS_0_REG,
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(TZC400_NSAID_RD_RW << 0) | /* CCI400 */
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(TZC400_NSAID_RD_RW << 1) | /* PCIE */
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(TZC400_NSAID_RD_RW << 2) | /* HDLCD0 */
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(TZC400_NSAID_RD_RW << 3) | /* HDLCD1 */
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(TZC400_NSAID_RD_RW << 4) | /* USB */
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(TZC400_NSAID_RD_RW << 5) | /* DMA330 */
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(TZC400_NSAID_RD_RW << 6) | /* THINLINKS */
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(TZC400_NSAID_RD_RW << 9) | /* AP */
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(TZC400_NSAID_RD_RW << 10) | /* GPU */
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(TZC400_NSAID_RD_RW << 11) | /* SCP */
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(TZC400_NSAID_RD_RW << 12) /* CORESIGHT */
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(TZC400_NSAID_RD_RW << TZC400_NSAID_CCI400) |
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(TZC400_NSAID_RD_RW << TZC400_NSAID_PCIE) |
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(TZC400_NSAID_RD_RW << TZC400_NSAID_HDLCD0) |
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(TZC400_NSAID_RD_RW << TZC400_NSAID_HDLCD1) |
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(TZC400_NSAID_RD_RW << TZC400_NSAID_USB) |
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(TZC400_NSAID_RD_RW << TZC400_NSAID_DMA330) |
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(TZC400_NSAID_RD_RW << TZC400_NSAID_THINLINKS) |
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(TZC400_NSAID_RD_RW << TZC400_NSAID_AP) |
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(TZC400_NSAID_RD_RW << TZC400_NSAID_GPU) |
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(TZC400_NSAID_RD_RW << TZC400_NSAID_SCP) |
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(TZC400_NSAID_RD_RW << TZC400_NSAID_CORESIGHT)
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);
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}
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@ -117,7 +117,6 @@
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/* Following covers Columbus Peripherals excluding NSROM and NSRAM */
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#define DEVICE0_BASE 0x20000000
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#define DEVICE0_SIZE 0x0e000000
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#define TZC400_BASE 0x2a4a0000
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#define MHU_BASE 0x2b1f0000
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#define NSRAM_BASE 0x2e000000
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@ -267,6 +266,24 @@
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#define SOC_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12)
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/*******************************************************************************
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* TZC-400 related constants
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******************************************************************************/
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#define TZC400_BASE 0x2a4a0000
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#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! HW fix in next revision */
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#define TZC400_NSAID_PCIE 1
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#define TZC400_NSAID_HDLCD0 2
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#define TZC400_NSAID_HDLCD1 3
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#define TZC400_NSAID_USB 4
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#define TZC400_NSAID_DMA330 5
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#define TZC400_NSAID_THINLINKS 6
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#define TZC400_NSAID_AP 9
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#define TZC400_NSAID_GPU 10
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#define TZC400_NSAID_SCP 11
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#define TZC400_NSAID_CORESIGHT 12
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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@ -29,6 +29,7 @@
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#
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PLAT_INCLUDES := -Idrivers/arm/interconnect/cci-400 \
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-Idrivers/arm/trustzone/tzc-400 \
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-Idrivers/arm/peripherals/pl011 \
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-Idrivers/power
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