feat(cpus): workaround for Cortex A78 AE erratum 1941500
Cortex A78 AE erratum 1941500 is a Cat B erratum that applies to revisions <= r0p1. It is still open. This erratum is avoided by by setting CPUECTLR_EL1[8] to 1. There is a small performance cost (<0.5%) for setting this bit. SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900 Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -283,6 +283,10 @@ For Cortex-A78, the following errata build flags are defined :
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For Cortex-A78 AE, the following errata build flags are defined :
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- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78
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AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
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still open.
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- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to Cortex-A78
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AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
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still open.
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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* Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -11,4 +12,10 @@
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#define CORTEX_A78_AE_MIDR U(0x410FD420)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1
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#define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8
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#endif /* CORTEX_A78_AE_H */
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@ -17,6 +17,36 @@
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#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for A78 AE Erratum 1941500.
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* This applies to revisions r0p0 and r0p1 of A78 AE.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_ae_1941500_wa
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/* Compare x0 against revisions r0p0 - r0p1 */
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mov x17, x30
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bl check_errata_1941500
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cbz x0, 1f
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/* Set bit 8 in ECTLR_EL1 */
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mrs x0, CORTEX_A78_AE_CPUECTLR_EL1
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bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
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msr CORTEX_A78_AE_CPUECTLR_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_a78_ae_1941500_wa
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func check_errata_1941500
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/* Applies to revisions r0p0 and r0p1. */
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mov x1, #CPU_REV(0, 0)
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mov x2, #CPU_REV(0, 1)
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b cpu_rev_var_range
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endfunc check_errata_1941500
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/* --------------------------------------------------
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* Errata Workaround for A78 AE Erratum 1951502.
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* This applies to revisions r0p0 and r0p1 of A78 AE.
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@ -78,6 +108,11 @@ func cortex_a78_ae_reset_func
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A78_AE_1941500
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mov x0, x18
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bl errata_a78_ae_1941500_wa
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#endif
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#if ERRATA_A78_AE_1951502
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mov x0, x18
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bl errata_a78_ae_1951502_wa
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@ -138,6 +173,7 @@ func cortex_a78_ae_errata_report
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
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report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
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ldp x8, x30, [sp], #16
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@ -311,6 +311,10 @@ ERRATA_A78_1941498 ?=0
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# well but there is no workaround for that revision.
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ERRATA_A78_1951500 ?=0
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# Flag to apply erratum 1941500 workaround during reset. This erratum applies
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# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
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ERRATA_A78_AE_1941500 ?=0
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# Flag to apply erratum 1951502 workaround during reset. This erratum applies
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# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
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ERRATA_A78_AE_1951502 ?=0
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@ -650,6 +654,10 @@ $(eval $(call add_define,ERRATA_A78_1941498))
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$(eval $(call assert_boolean,ERRATA_A78_1951500))
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$(eval $(call add_define,ERRATA_A78_1951500))
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# Process ERRATA_A78_AE_1941500 flag
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$(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
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$(eval $(call add_define,ERRATA_A78_AE_1941500))
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# Process ERRATA_A78_AE_1951502 flag
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$(eval $(call assert_boolean,ERRATA_A78_AE_1951502))
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$(eval $(call add_define,ERRATA_A78_AE_1951502))
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