From eca6e45336d81d924948bcff2f3db8488252f17b Mon Sep 17 00:00:00 2001 From: Sami Mujawar Date: Fri, 10 May 2019 14:28:37 +0100 Subject: [PATCH 1/4] Disable speculative loads only if SSBS is supported Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative loads (SSBS) is implemented, before disabling speculative loads. Change-Id: I7607c45ed2889260d22a94f6fd9af804520acf67 Signed-off-by: Sami Mujawar --- lib/cpus/aarch64/neoverse_n1.S | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 2038f318b..a0babb0ef 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -49,11 +49,31 @@ func check_errata_1043202 b cpu_rev_var_ls endfunc check_errata_1043202 +/* -------------------------------------------------- + * Disable speculative loads if Neoverse N1 supports + * SSBS. + * + * Shall clobber: x0. + * -------------------------------------------------- + */ +func neoverse_n1_disable_speculative_loads + /* Check if the PE implements SSBS */ + mrs x0, id_aa64pfr1_el1 + tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) + b.eq 1f + + /* Disable speculative loads */ + msr SSBS, xzr + isb + +1: + ret +endfunc neoverse_n1_disable_speculative_loads + func neoverse_n1_reset_func mov x19, x30 - /* Disables speculative loads */ - msr SSBS, xzr + bl neoverse_n1_disable_speculative_loads /* Forces all cacheable atomic instructions to be near */ mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 From 6bb6015f915dbc6a1208358024387a76530d45da Mon Sep 17 00:00:00 2001 From: Sami Mujawar Date: Thu, 9 May 2019 13:35:02 +0100 Subject: [PATCH 2/4] Add option for defining platform DRAM2 base The default DRAM2 base address for Arm platforms is 0x880000000. However, on some platforms the firmware may want to move the start address to a different value. To support this introduce PLAT_ARM_DRAM2_BASE that defaults to 0x880000000; but can be overridden by a platform (e.g. in platform_def.h). Change-Id: I0d81195e06070bc98f376444b48ada2db1666e28 Signed-off-by: Sami Mujawar --- include/plat/arm/board/common/board_css_def.h | 4 ++-- include/plat/arm/common/arm_def.h | 4 ++-- plat/arm/board/fvp/include/platform_def.h | 1 + plat/arm/board/fvp_ve/include/platform_def.h | 3 ++- 4 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h index 452afbcc8..f982b57b4 100644 --- a/include/plat/arm/board/common/board_css_def.h +++ b/include/plat/arm/board/common/board_css_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -54,7 +54,7 @@ * Required platform porting definitions common to all ARM CSS-based * development platforms */ - +#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) /* UART related constants */ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 62623c1bf..69a9959ad 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -148,7 +148,7 @@ #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ ARM_DRAM1_SIZE - 1) -#define ARM_DRAM2_BASE UL(0x880000000) +#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ ARM_DRAM2_SIZE - 1) diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 6856a286f..2313ab0c2 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -48,6 +48,7 @@ /* No SCP in FVP */ #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) +#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) /* diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h index 1870442f0..1b21c79d1 100644 --- a/plat/arm/board/fvp_ve/include/platform_def.h +++ b/plat/arm/board/fvp_ve/include/platform_def.h @@ -25,7 +25,7 @@ #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ ARM_DRAM1_SIZE - 1) -#define ARM_DRAM2_BASE UL(0x880000000) +#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ ARM_DRAM2_SIZE - 1) @@ -230,6 +230,7 @@ #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ +#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) /* From 49d64e5d0e8d63dadc3efb1b32579973dd677c41 Mon Sep 17 00:00:00 2001 From: Sami Mujawar Date: Thu, 9 May 2019 13:43:30 +0100 Subject: [PATCH 3/4] N1SDP: Fix DRAM2 start address The default DRAM2 start address for Arm platforms is 0x880000000. However, for N1SDP platform this is 0x8080000000. Fix the DRAM2 start address by initialising PLAT_ARM_DRAM2_BASE. Without this fix there is a mismatch of the System memory region view as seen by the BL31 runtime firmware (PSCI) versus the view of the OS (which is based on the description provided by UEFI. In this case UEFI is correctly describing the DRAM2 start address). This implicates in secondary cores failing to start on some Operating Systems if the OS decides to place the secondary start address in the mismatched region. Change-Id: I57220e753219353dda429868b4c5e1a69944cc64 Signed-off-by: Sami Mujawar --- plat/arm/board/n1sdp/include/platform_def.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h index adb957e5d..0964f5688 100644 --- a/plat/arm/board/n1sdp/include/platform_def.h +++ b/plat/arm/board/n1sdp/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,6 +24,7 @@ #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ +#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) #if CSS_USE_SCMI_SDS_DRIVER From 603b372e5349ef4bfc2fbea395787d64620a73d3 Mon Sep 17 00:00:00 2001 From: Sami Mujawar Date: Fri, 10 May 2019 08:52:07 +0100 Subject: [PATCH 4/4] N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN N1SDP exhibits the behavior similar to Juno wherein CNTBaseN.CNTFRQ can be written but does not reflect the value of the CNTFRQ register in CNTCTLBase frame. This doesn't follow ARM ARM in that the value updated in CNTCTLBase.CNTFRQ is not reflected in CNTBaseN.CNTFRQ. Hence enable the workaround (applied to Juno) for N1SDP that updates the CNTFRQ register in the Non Secure CNTBaseN frame. Change-Id: Id89ee1bca0f25c9d62f8f794f2c4f4e618cdf092 Signed-off-by: Sami Mujawar --- plat/arm/common/arm_common.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 0442945b8..f5ce4d241 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -127,12 +127,12 @@ void arm_configure_sys_timer(void) */ mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); -#ifdef PLAT_juno +#if defined(PLAT_juno) || defined(PLAT_n1sdp) /* * Initialize CNTFRQ register in Non-secure CNTBase frame. - * This is only required for Juno, because it doesn't follow ARM ARM - * in that the value updated in CNTFRQ is not reflected in - * CNTBASEN_CNTFRQ. Hence update the value manually. + * This is only required for Juno and N1SDP, because they do not + * follow ARM ARM in that the value updated in CNTFRQ is not + * reflected in CNTBASEN_CNTFRQ. Hence update the value manually. */ mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val); #endif