docs: Fixes and updates for the v2.3 release

A small set of misc changes to ensure correctness before the v2.3
release.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I5b4e35b3b46616df0453cecff61f5a414951cd62
This commit is contained in:
laurenw-arm 2020-04-15 17:48:36 -05:00
parent cc52800db4
commit 495553d572
3 changed files with 13 additions and 16 deletions

View File

@ -86,8 +86,8 @@ Current features
in ROM but is accessed through a jump-table that may be stored in ROM but is accessed through a jump-table that may be stored
in read-write memory, allowing for the library code to be patched. in read-write memory, allowing for the library code to be patched.
- A prototype implementation of a Secure Partition Manager (SPM) that is based - Support for the Secure Partition Manager Dispatcher (SPMD) component as a
on the SPCI Alpha 1 and SPRT draft specifications. new standard service.
- Support for ARMv8.3 pointer authentication in the normal and secure worlds. - Support for ARMv8.3 pointer authentication in the normal and secure worlds.
The use of pointer authentication in the normal world is enabled whenever The use of pointer authentication in the normal world is enabled whenever
@ -96,8 +96,8 @@ Current features
experimental configuration at this time and requires the experimental configuration at this time and requires the
``BRANCH_PROTECTION`` option to be set to non-zero. ``BRANCH_PROTECTION`` option to be set to non-zero.
- Position-Independent Executable (PIE) support. Initially for BL31 only, with - Position-Independent Executable (PIE) support. Currently for BL2, BL31, and
further support to be added in a future release. TSP, with further support to be added in a future release.
Still to come Still to come
------------- -------------
@ -124,4 +124,4 @@ Still to come
-------------- --------------
*Copyright (c) 2019, Arm Limited. All rights reserved.* *Copyright (c) 2020, Arm Limited. All rights reserved.*

View File

@ -17,8 +17,6 @@ Main maintainers
:G: `sandrine-bailleux-arm`_ :G: `sandrine-bailleux-arm`_
:M: Alexei Fedorov <alexei.fedorov@arm.com> :M: Alexei Fedorov <alexei.fedorov@arm.com>
:G: `AlexeiFedorov`_ :G: `AlexeiFedorov`_
:M: György Szing <gyorgy.szing@arm.com>
:G: `gyuri-szing`_
:M: Manish Pandey <manish.pandey2@arm.com> :M: Manish Pandey <manish.pandey2@arm.com>
:G: `manish-pandey-arm`_ :G: `manish-pandey-arm`_
:M: Mark Dykes <mark.dykes@arm.com> :M: Mark Dykes <mark.dykes@arm.com>
@ -311,7 +309,6 @@ Xilinx platform port
.. _etienne-lms: https://github.com/etienne-lms .. _etienne-lms: https://github.com/etienne-lms
.. _glneo: https://github.com/glneo .. _glneo: https://github.com/glneo
.. _grandpaul: https://github.com/grandpaul .. _grandpaul: https://github.com/grandpaul
.. _gyuri-szing: https://github.com/gyuri-szing
.. _hzhuang1: https://github.com/hzhuang1 .. _hzhuang1: https://github.com/hzhuang1
.. _JackyBai: https://github.com/JackyBai .. _JackyBai: https://github.com/JackyBai
.. _jenswi-linaro: https://github.com/jenswi-linaro .. _jenswi-linaro: https://github.com/jenswi-linaro

View File

@ -12,7 +12,7 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores
(64-bit host machine only). (64-bit host machine only).
.. note:: .. note::
The FVP models used are Version 11.6 Build 45, unless otherwise stated. The FVP models used are Version 11.9 Build 41, unless otherwise stated.
- ``FVP_Base_AEMv8A-AEMv8A`` - ``FVP_Base_AEMv8A-AEMv8A``
- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
@ -26,8 +26,8 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores
- ``FVP_Base_Cortex-A57x2-A53x4`` - ``FVP_Base_Cortex-A57x2-A53x4``
- ``FVP_Base_Cortex-A57x4-A53x4`` - ``FVP_Base_Cortex-A57x4-A53x4``
- ``FVP_Base_Cortex-A57x4`` - ``FVP_Base_Cortex-A57x4``
- ``FVP_Base_Cortex-A65x4`` (Version 11.9 build 41) - ``FVP_Base_Cortex-A65x4``
- ``FVP_Base_Cortex-A65AEx8`` (Version 11.9 build 41) - ``FVP_Base_Cortex-A65AEx8``
- ``FVP_Base_Cortex-A72x4-A53x4`` - ``FVP_Base_Cortex-A72x4-A53x4``
- ``FVP_Base_Cortex-A72x4`` - ``FVP_Base_Cortex-A72x4``
- ``FVP_Base_Cortex-A73x4-A53x4`` - ``FVP_Base_Cortex-A73x4-A53x4``
@ -36,13 +36,13 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores
- ``FVP_Base_Cortex-A76x4`` - ``FVP_Base_Cortex-A76x4``
- ``FVP_Base_Cortex-A76AEx4`` - ``FVP_Base_Cortex-A76AEx4``
- ``FVP_Base_Cortex-A76AEx8`` - ``FVP_Base_Cortex-A76AEx8``
- ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) - ``FVP_Base_Cortex-A77x4``
- ``FVP_Base_Neoverse-N1x4`` - ``FVP_Base_Neoverse-N1x4``
- ``FVP_Base_Zeusx4`` - ``FVP_Base_Zeusx4``
- ``FVP_CSS_SGI-575`` (Version 11.3 build 42) - ``FVP_CSS_SGI-575`` (Version 11.10 build 25)
- ``FVP_CSS_SGM-775`` (Version 11.3 build 42) - ``FVP_CSS_SGM-775``
- ``FVP_RD_E1Edge`` (Version 11.3 build 42) - ``FVP_RD_E1Edge``
- ``FVP_RD_N1Edge`` - ``FVP_RD_N1Edge`` (Version 11.10 build 25)
- ``Foundation_Platform`` - ``Foundation_Platform``
The latest version of the AArch32 build of TF-A has been tested on the The latest version of the AArch32 build of TF-A has been tested on the