Merge changes from topic "nonbl2-boot" into integration
* changes: intel: stratix10: Modify BL31 parameter handling intel: Modify BL31 address mapping intel: stratix10: Enable uboot entrypoint support
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commit
4962385ec2
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@ -8,6 +8,7 @@
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <platform_def.h>
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#include <el3_common_macros.S>
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.globl plat_secondary_cold_boot_setup
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.globl platform_is_primary_cpu
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@ -17,6 +18,7 @@
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl plat_secondary_cpus_bl31_entry
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.globl plat_get_my_entrypoint
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@ -33,7 +35,6 @@ func plat_secondary_cold_boot_setup
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/* Wait until the it gets reset signal from rstmgr gets populated */
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poll_mailbox:
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wfi
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mov_imm x0, PLAT_SEC_ENTRY
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ldr x1, [x0]
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mov_imm x2, PLAT_CPUID_RELEASE
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@ -114,3 +115,14 @@ func platform_mem_init
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mov x0, #0
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ret
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endfunc platform_mem_init
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func plat_secondary_cpus_bl31_entry
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el3_entrypoint_common \
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_init_sctlr=0 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=runtime_exceptions \
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_pie_fixup_size=BL31_LIMIT - BL31_BASE
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endfunc plat_secondary_cpus_bl31_entry
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@ -16,8 +16,8 @@
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#define PLAT_SOCFPGA_STRATIX10 1
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#define PLAT_SOCFPGA_AGILEX 2
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#define PLAT_CPUID_RELEASE 0xffe1b000
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#define PLAT_SEC_ENTRY 0xffe1b008
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/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
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#define PLAT_CPU_RELEASE_ADDR 0xffd12210
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/* Define next boot image name and offset */
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#define PLAT_NS_IMAGE_OFFSET 0x50000
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@ -117,8 +117,13 @@
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#define BL2_BASE (0xffe00000)
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#define BL2_LIMIT (0xffe1b000)
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#define BL31_BASE (0xffe1c000)
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#define BL31_LIMIT (0xffe3bfff)
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#define BL31_BASE (0x1000)
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#define BL31_LIMIT (0x81000)
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#define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET
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#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16)
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#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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@ -194,5 +199,16 @@
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#define MAX_IO_DEVICES 4
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#define MAX_IO_BLOCK_DEVICES 2
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#ifndef __ASSEMBLER__
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struct socfpga_bl31_params {
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param_header_t h;
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image_info_t *bl31_image_info;
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entry_point_info_t *bl32_ep_info;
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image_info_t *bl32_image_info;
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entry_point_info_t *bl33_ep_info;
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image_info_t *bl33_image_info;
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};
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#endif
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#endif /* PLATFORM_DEF_H */
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@ -61,5 +61,6 @@ uint32_t socfpga_get_spsr_for_bl33_entry(void);
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unsigned long socfpga_get_ns_image_entrypoint(void);
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void plat_secondary_cpus_bl31_entry(void);
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#endif /* SOCFPGA_PRIVATE_H */
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@ -15,8 +15,6 @@
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#include "socfpga_plat_def.h"
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uintptr_t *socfpga_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
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uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
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/*******************************************************************************
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* plat handler called when a CPU is about to enter standby.
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@ -45,7 +43,7 @@ int socfpga_pwr_domain_on(u_register_t mpidr)
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if (cpu_id == -1)
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return PSCI_E_INTERN_FAIL;
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*cpuid_release = cpu_id;
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mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
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/* release core reset */
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mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
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@ -183,8 +181,8 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const struct plat_psci_ops **psci_ops)
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{
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/* Save warm boot entrypoint.*/
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*socfpga_sec_entry = sec_entrypoint;
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mmio_write_64(PLAT_SEC_ENTRY, sec_entrypoint);
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*psci_ops = &socfpga_psci_pm_ops;
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return 0;
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}
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@ -53,16 +53,16 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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void *from_bl2 = (void *) arg0;
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bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
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assert(params_from_bl2 != NULL);
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assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
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assert(params_from_bl2->h.version >= VERSION_2);
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/*
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* Copy BL32 (if populated by BL31) and BL33 entry point information.
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* They are stored in Secure RAM, in BL31's address space.
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*/
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if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
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params_from_bl2->h.version >= VERSION_2) {
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bl_params_node_t *bl_params = params_from_bl2->head;
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while (bl_params) {
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@ -71,6 +71,16 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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bl_params = bl_params->next_params_info;
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}
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} else {
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struct socfpga_bl31_params *arg_from_bl2 =
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(struct socfpga_bl31_params *) from_bl2;
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assert(arg_from_bl2->h.type == PARAM_BL31);
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assert(arg_from_bl2->h.version >= VERSION_1);
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bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
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bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
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}
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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}
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@ -100,6 +110,10 @@ void bl31_platform_setup(void)
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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/* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
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mmio_write_64(PLAT_CPU_RELEASE_ADDR,
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(uint64_t)plat_secondary_cpus_bl31_entry);
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}
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const mmap_region_t plat_stratix10_mmap[] = {
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