From 4988c4c1652c3e3af5d42a0343daee80c2c7e023 Mon Sep 17 00:00:00 2001 From: Chiaki Fujii Date: Fri, 1 Mar 2019 20:28:55 +0900 Subject: [PATCH] rcar_gen3: drivers: ddr: Update DDR setting rev.0.35 [IPL/DDR] - Update DDR setting rev.0.35. Signed-off-by: Chiaki Fujii Change-Id: I2b936ca8621ca320cc97353f99240da5f24781f7 --- .../renesas/rcar/ddr/ddr_b/boot_init_dram.c | 97 ++++++++++++------- .../rcar/ddr/ddr_b/boot_init_dram_config.c | 58 ++++++++++- .../rcar/ddr/ddr_b/boot_init_dram_regdef.h | 4 +- .../rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h | 6 +- .../renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h | 6 +- .../rcar/ddr/ddr_b/init_dram_tbl_m3n.h | 6 +- 6 files changed, 129 insertions(+), 48 deletions(-) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index f88de8301..16581bdc6 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -95,7 +95,6 @@ static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; static uint32_t max_density; static uint32_t ddr0800_mul; static uint32_t ddr_mul; -static uint32_t ddr_mbps; static uint32_t DDR_PHY_SLICE_REGSET_OFS; static uint32_t DDR_PHY_ADR_V_REGSET_OFS; static uint32_t DDR_PHY_ADR_I_REGSET_OFS; @@ -1136,6 +1135,7 @@ static void regif_pll_wa(void) uint32_t ch; if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + // PLL setting for PHY : H3 Ver.1.x reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), (0x0064U << ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); @@ -1175,6 +1175,9 @@ static void regif_pll_wa(void) _reg_PHY_LP4_BOOT_TOP_PLL_CTRL)); } + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), + _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]); + /* protect register interface */ ddrphy_regif_idle(); pll3_control(0); @@ -1902,7 +1905,14 @@ static void ddr_config(void) CACS DLY ***********************************************************************/ dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); - set_dfifrequency(0x1f); + + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + set_dfifrequency(0x1f); + } else { + ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00); + ddr_setval_ach(_reg_PHY_FREQ_SEL_INDEX, 0x01); + } + foreach_vch(ch) { int16_t adj; for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { @@ -1921,7 +1931,13 @@ static void ddr_config(void) } } } - set_dfifrequency(0x00); + + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + set_dfifrequency(0x00); + } else { + ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x01); + ddr_setval_ach(_reg_PHY_FREQ_SEL_INDEX, 0x00); + } /*********************************************************************** WDQDM DLY @@ -2234,7 +2250,16 @@ static void dbsc_regset(void) + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; if (tmp[0] < dataL) tmp[0] = dataL; - mmio_write_32(DBSC_DBSCHRW1, tmp[0]); + + if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { + mmio_write_32(DBSC_DBSCHRW1, tmp[0] + + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + * 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps - 3); + } else { + mmio_write_32(DBSC_DBSCHRW1, tmp[0] + + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + * 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps); + } /*********************************************************************** QOS and CAM @@ -2378,6 +2403,38 @@ static void dbsc_regset_post(void) dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff)); mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) { +#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */ + PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1); + send_dbcmd(0x08040001); + wait_dbcmd(); + send_dbcmd(0x0A040001); + wait_dbcmd(); + send_dbcmd(0x04040010); + wait_dbcmd(); + + if (Prr_Product == PRR_PRODUCT_H3) { + send_dbcmd(0x08140001); + wait_dbcmd(); + send_dbcmd(0x0A140001); + wait_dbcmd(); + send_dbcmd(0x04140010); + wait_dbcmd(); + } +#else /* DDR_BACKUPMODE_HALF //for All channels */ + send_dbcmd(0x08840001); + wait_dbcmd(); + send_dbcmd(0x0A840001); + wait_dbcmd(); + + send_dbcmd(0x04840010); + wait_dbcmd(); +#endif /* DDR_BACKUPMODE_HALF */ + } +#endif /* DDR_BACKUPMODE */ + #if RCAR_REWT_TRAINING != 0 /* Periodic-WriteDQ Training seeting */ if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) @@ -2433,37 +2490,6 @@ static void dbsc_regset_post(void) #endif /* RCAR_DRAM_SPLIT == 2 */ } -#ifdef DDR_BACKUPMODE - if (ddrBackup == DRAM_BOOT_STATUS_WARM) { -#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */ - PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1); - send_dbcmd(0x08040001); - wait_dbcmd(); - send_dbcmd(0x0A040001); - wait_dbcmd(); - send_dbcmd(0x04040010); - wait_dbcmd(); - - if (Prr_Product == PRR_PRODUCT_H3) { - send_dbcmd(0x08140001); - wait_dbcmd(); - send_dbcmd(0x0A140001); - wait_dbcmd(); - send_dbcmd(0x04140010); - wait_dbcmd(); - } -#else /* DDR_BACKUPMODE_HALF //for All channels */ - send_dbcmd(0x08840001); - wait_dbcmd(); - send_dbcmd(0x0A840001); - wait_dbcmd(); - - send_dbcmd(0x04840010); - wait_dbcmd(); -#endif /* DDR_BACKUPMODE_HALF */ - } -#endif /* DDR_BACKUPMODE */ - mmio_write_32(DBSC_DBRFEN, 0x00000001); /* dram access enable */ mmio_write_32(DBSC_DBACEN, 0x00000001); @@ -3104,6 +3130,7 @@ static uint32_t init_ddr(void) /*********************************************************************** exec pi_training ***********************************************************************/ + ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00); ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index 43978c26c..513bb0357 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#define BOARDNUM 19 +#define BOARDNUM 20 #define BOARD_JUDGE_AUTO #ifdef BOARD_JUDGE_AUTO @@ -1374,6 +1374,57 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = { } } }, +/* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */ + { + 0x03, + 0x01, + 0x02c0, + 0, + 0x0300, + 0x00a0, + { + { + {0x04, 0xff}, + 0x00543210, + 0x3201, + {0x70612543, 0x43251670, 0x45326170, 0x10672534}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + }, + { + {0x04, 0xff}, + 0x00543210, + 0x2310, + {0x01327654, 0x34526107, 0x35421670, 0x70615324}, + {0x08, 0x08, 0x08, 0x08}, + WDQLVL_PAT, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0} + } + } + }, }; void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div) @@ -1618,9 +1669,12 @@ static uint32_t _board_judge(void) } else if (Prr_Product == PRR_PRODUCT_M3N) { /* RENESAS SALVATOR-X (M3-N/SIP) */ brd = 11; - } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { + } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20)) { /* RENESAS SALVATOR-X (M3-W/SIP) */ brd = 0; + } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { + /* RENESAS SALVATOR-X (M3-W Ver.1.3/SIP) */ + brd = 19; } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) { /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */ brd = 18; diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h index 6a3d1c078..24ff83395 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h @@ -1,10 +1,10 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#define RCAR_DDR_VERSION "rev.0.35rc01" +#define RCAR_DDR_VERSION "rev.0.35" #define DRAM_CH_CNT (0x04) #define SLICE_CNT (0x04) #define CS_CNT (0x02) diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h index 2e464010d..6e4c30eb8 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -239,8 +239,8 @@ static const uint32_t /*069d*/ 0x0002c000, /*069e*/ 0x02c002c0, /*069f*/ 0x000002c0, -/*06a0*/ 0x01421142, -/*06a1*/ 0x00000142, +/*06a0*/ 0x03421342, +/*06a1*/ 0x00000342, /*06a2*/ 0x00000000, /*06a3*/ 0x00000000, /*06a4*/ 0x05020000, diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h index 1762298f5..3c62107ed 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -219,8 +219,8 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = { /*0b95*/ 0x0002c000, /*0b96*/ 0x02c002c0, /*0b97*/ 0x000002c0, -/*0b98*/ 0x01421142, -/*0b99*/ 0x00000142, +/*0b98*/ 0x03421342, +/*0b99*/ 0x00000342, /*0b9a*/ 0x00000000, /*0b9b*/ 0x00000000, /*0b9c*/ 0x05020000, diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h index a9569ee2f..42c335196 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -240,8 +240,8 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = { /*0b9e*/ 0x02c002c0, /*0b9f*/ 0x000002c0, /*0ba0*/ 0x08040201, -/*0ba1*/ 0x01421142, -/*0ba2*/ 0x00000142, +/*0ba1*/ 0x03421342, +/*0ba2*/ 0x00000342, /*0ba3*/ 0x00000000, /*0ba4*/ 0x00000000, /*0ba5*/ 0x05030000,