mediatek: mt8192: add timer support
add timer driver. Signed-off-by: Dehui Sun <dehui.sun@mediatek.com> Change-Id: I07448d85a15bb14577b05e4f302860d609420ba7
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <mt_timer.h>
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#include <platform_def.h>
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uint64_t normal_time_base;
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uint64_t atf_time_base;
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void sched_clock_init(uint64_t normal_base, uint64_t atf_base)
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{
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normal_time_base += normal_base;
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atf_time_base = atf_base;
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}
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uint64_t sched_clock(void)
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{
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uint64_t cval;
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uint64_t rel_base;
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rel_base = read_cntpct_el0() - atf_time_base;
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cval = ((rel_base * 1000U) / SYS_COUNTER_FREQ_IN_MHZ)
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- normal_time_base;
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return cval;
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}
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/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MT_TIMER_H
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#define MT_TIMER_H
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#define SYSTIMER_BASE (0x10017000)
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#define CNTCR_REG (SYSTIMER_BASE + 0x0)
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#define CNTSR_REG (SYSTIMER_BASE + 0x4)
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#define CNTSYS_L_REG (SYSTIMER_BASE + 0x8)
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#define CNTSYS_H_REG (SYSTIMER_BASE + 0xc)
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#define TIEO_EN (1 << 3)
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#define COMP_15_EN (1 << 10)
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#define COMP_20_EN (1 << 11)
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#define COMP_25_EN (1 << 12)
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#define COMP_FEATURE_MASK (COMP_15_EN | COMP_20_EN | COMP_25_EN | TIEO_EN)
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#define COMP_15_MASK (COMP_15_EN)
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#define COMP_20_MASK (COMP_20_EN | TIEO_EN)
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#define COMP_25_MASK (COMP_20_EN | COMP_25_EN)
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void sched_clock_init(uint64_t normal_base, uint64_t atf_base);
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uint64_t sched_clock(void);
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#endif /* MT_TIMER_H */
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@ -10,7 +10,8 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
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PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
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-I${MTK_PLAT_SOC}/include/ \
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-I${MTK_PLAT_SOC}/drivers/ \
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-I${MTK_PLAT_SOC}/drivers/gpio/
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-I${MTK_PLAT_SOC}/drivers/gpio/ \
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-I${MTK_PLAT_SOC}/drivers/timer/
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GICV3_SUPPORT_GIC600 := 1
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include drivers/arm/gic/v3/gicv3.mk
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${MTK_PLAT_SOC}/plat_topology.c \
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${MTK_PLAT_SOC}/plat_mt_gic.c \
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${MTK_PLAT_SOC}/plat_mt_cirq.c \
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${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c
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${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
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${MTK_PLAT_SOC}/drivers/timer/mt_timer.c
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# Configs for A76 and A55
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