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Merge pull request #800 from masahir0y/ifdef 

Correct preprocessor conditionals
This commit is contained in:
danh-arm 2017-01-23 16:49:43 +00:00 committed by GitHub
parent e02be20722 6af03f9c45
commit 4abd2225c2
23 changed files with 76 additions and 75 deletions
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6
drivers/arm/ccn/ccn.c
View File

@ -38,7 +38,7 @@
#include "ccn_private.h"
static const ccn_desc_t *ccn_plat_desc;
#if IMAGE_BL31
#ifdef IMAGE_BL31
DEFINE_BAKERY_LOCK(ccn_lock);
#endif
@ -285,7 +285,7 @@ static void ccn_snoop_dvm_do_op(unsigned long long rn_id_map,
assert(ccn_plat_desc);
assert(ccn_plat_desc->periphbase);
#if IMAGE_BL31
#ifdef IMAGE_BL31
bakery_lock_get(&ccn_lock);
#endif
start_region_id = region_id;
@ -305,7 +305,7 @@ static void ccn_snoop_dvm_do_op(unsigned long long rn_id_map,
rn_id_map);
}
#if IMAGE_BL31
#ifdef IMAGE_BL31
bakery_lock_release(&ccn_lock);
#endif
}

4
include/common/aarch32/el3_common_macros.S
View File

@ -228,7 +228,7 @@
* ---------------------------------------------------------------------
*/
.if \_init_c_runtime
#if IMAGE_BL32
#ifdef IMAGE_BL32
/* -----------------------------------------------------------------
* Invalidate the RW memory used by the BL32 (SP_MIN) image. This
* includes the data and NOBITS sections. This is done to
@ -253,7 +253,7 @@
bl zeromem
#endif
#if IMAGE_BL1
#ifdef IMAGE_BL1
/* -----------------------------------------------------
* Copy data from ROM to RAM.
* -----------------------------------------------------

6
include/common/aarch64/el3_common_macros.S
View File

@ -49,7 +49,7 @@
msr sctlr_el3, x0
isb
#if IMAGE_BL31
#ifdef IMAGE_BL31
/* ---------------------------------------------------------------------
* Initialise the per-cpu cache pointer to the CPU.
* This is done early to enable crash reporting to have access to crash
@ -235,7 +235,7 @@
* ---------------------------------------------------------------------
*/
.if \_init_c_runtime
#if IMAGE_BL31
#ifdef IMAGE_BL31
/* -------------------------------------------------------------
* Invalidate the RW memory used by the BL31 image. This
* includes the data and NOBITS sections. This is done to
@ -260,7 +260,7 @@
bl zeromem16
#endif
#if IMAGE_BL1
#ifdef IMAGE_BL1
ldr x0, =__DATA_RAM_START__
ldr x1, =__DATA_ROM_START__
ldr x2, =__DATA_SIZE__

8
include/common/bl_common.h
View File

@ -170,13 +170,13 @@ extern uintptr_t __RO_START__;
extern uintptr_t __RO_END__;
#endif
#if IMAGE_BL2
#if defined(IMAGE_BL2)
extern uintptr_t __BL2_END__;
#elif IMAGE_BL2U
#elif defined(IMAGE_BL2U)
extern uintptr_t __BL2U_END__;
#elif IMAGE_BL31
#elif defined(IMAGE_BL31)
extern uintptr_t __BL31_END__;
#elif IMAGE_BL32
#elif defined(IMAGE_BL32)
extern uintptr_t __BL32_END__;
#endif /* IMAGE_BLX */

8
include/lib/cpus/aarch32/cpu_macros.S
View File

@ -51,11 +51,11 @@
CPU_MIDR: /* cpu_ops midr */
.space 4
/* Reset fn is needed during reset */
#if IMAGE_BL1 || IMAGE_BL32
#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
CPU_RESET_FUNC: /* cpu_ops reset_func */
.space 4
#endif
#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
#ifdef IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
CPU_PWR_DWN_OPS: /* cpu_ops power down functions */
.space (4 * CPU_MAX_PWR_DWN_OPS)
#endif
@ -117,10 +117,10 @@ CPU_OPS_SIZE = .
.align 2
.type cpu_ops_\_name, %object
.word \_midr
#if IMAGE_BL1 || IMAGE_BL32
#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
.word \_resetfunc
#endif
#if IMAGE_BL32
#ifdef IMAGE_BL32
1:
/* Insert list of functions */
fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops

12
include/lib/cpus/aarch64/cpu_macros.S
View File

@ -51,15 +51,15 @@
CPU_MIDR: /* cpu_ops midr */
.space 8
/* Reset fn is needed in BL at reset vector */
#if IMAGE_BL1 || IMAGE_BL31
#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
CPU_RESET_FUNC: /* cpu_ops reset_func */
.space 8
#endif
#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
CPU_PWR_DWN_OPS: /* cpu_ops power down functions */
.space (8 * CPU_MAX_PWR_DWN_OPS)
#endif
#if (IMAGE_BL31 && CRASH_REPORTING)
#if defined(IMAGE_BL31) && CRASH_REPORTING
CPU_REG_DUMP: /* cpu specific register dump for crash reporting */
.space 8
#endif
@ -121,10 +121,10 @@ CPU_OPS_SIZE = .
.align 3
.type cpu_ops_\_name, %object
.quad \_midr
#if IMAGE_BL1 || IMAGE_BL31
#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
.quad \_resetfunc
#endif
#if IMAGE_BL31
#ifdef IMAGE_BL31
1:
/* Insert list of functions */
fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
@ -141,7 +141,7 @@ CPU_OPS_SIZE = .
.endif
.endif
#endif
#if (IMAGE_BL31 && CRASH_REPORTING)
#if defined(IMAGE_BL31) && CRASH_REPORTING
.quad \_name\()_cpu_reg_dump
#endif
.endm

12
include/plat/arm/board/common/board_arm_def.h
View File

@ -39,23 +39,23 @@
*/
/* Size of cacheable stacks */
#if IMAGE_BL1
#if defined(IMAGE_BL1)
#if TRUSTED_BOARD_BOOT
# define PLATFORM_STACK_SIZE 0x1000
#else
# define PLATFORM_STACK_SIZE 0x440
#endif
#elif IMAGE_BL2
#elif defined(IMAGE_BL2)
# if TRUSTED_BOARD_BOOT
# define PLATFORM_STACK_SIZE 0x1000
# else
# define PLATFORM_STACK_SIZE 0x400
# endif
#elif IMAGE_BL2U
#elif defined(IMAGE_BL2U)
# define PLATFORM_STACK_SIZE 0x200
#elif IMAGE_BL31
#elif defined(IMAGE_BL31)
# define PLATFORM_STACK_SIZE 0x400
#elif IMAGE_BL32
#elif defined(IMAGE_BL32)
# define PLATFORM_STACK_SIZE 0x440
#endif
@ -73,7 +73,7 @@
* Optimisation is less important for the other, transient boot images so a
* common, maximum value is used across these images.
*/
#if IMAGE_BL31 || IMAGE_BL32
#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES 6
# define MAX_XLAT_TABLES 4
#else

2
include/plat/arm/common/plat_arm.h
View File

@ -64,7 +64,7 @@ void arm_setup_page_tables(uintptr_t total_base,
#endif
);
#if IMAGE_BL31
#ifdef IMAGE_BL31
/*
* Use this macro to instantiate lock before it is used in below
* arm_lock_xxx() macros

4
lib/cpus/aarch32/cpu_helpers.S
View File

@ -34,7 +34,7 @@
#include <cpu_data.h>
#include <cpu_macros.S>
#if IMAGE_BL1 || IMAGE_BL32
#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
/*
* The reset handler common to all platforms. After a matching
* cpu_ops structure entry is found, the correponding reset_handler
@ -68,7 +68,7 @@ endfunc reset_handler
#endif /* IMAGE_BL1 || IMAGE_BL32 */
#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
#ifdef IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
/*
* void prepare_cpu_pwr_dwn(unsigned int power_level)
*

8
lib/cpus/aarch64/cpu_helpers.S
View File

@ -31,14 +31,14 @@
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
#if IMAGE_BL31
#ifdef IMAGE_BL31
#include <cpu_data.h>
#endif
#include <cpu_macros.S>
#include <debug.h>
/* Reset fn is needed in BL at reset vector */
#if IMAGE_BL1 || IMAGE_BL31
#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
/*
* The reset handler common to all platforms. After a matching
* cpu_ops structure entry is found, the correponding reset_handler
@ -72,7 +72,7 @@ endfunc reset_handler
#endif /* IMAGE_BL1 || IMAGE_BL31 */
#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
/*
* void prepare_cpu_pwr_dwn(unsigned int power_level)
*
@ -130,7 +130,7 @@ func init_cpu_ops
endfunc init_cpu_ops
#endif /* IMAGE_BL31 */
#if IMAGE_BL31 && CRASH_REPORTING
#if defined(IMAGE_BL31) && CRASH_REPORTING
/*
* The cpu specific registers which need to be reported in a crash
* are reported via cpu_ops cpu_reg_dump function. After a matching

2
lib/el3_runtime/aarch64/context_mgmt.c
View File

@ -116,7 +116,7 @@ static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t
scr_el3 &= ~SCR_EA_BIT;
#endif
#if IMAGE_BL31
#ifdef IMAGE_BL31
/*
* IRQ/FIQ bits only need setting if interrupt routing
* model has been set up for BL31.

10
plat/arm/board/common/board_css_common.c
View File

@ -35,7 +35,7 @@
* This doesn't include Trusted SRAM as arm_setup_page_tables() already
* takes care of mapping it.
*/
#if IMAGE_BL1
#ifdef IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_FLASH0_RO,
@ -48,7 +48,7 @@ const mmap_region_t plat_arm_mmap[] = {
{0}
};
#endif
#if IMAGE_BL2
#ifdef IMAGE_BL2
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_FLASH0_RO,
@ -60,7 +60,7 @@ const mmap_region_t plat_arm_mmap[] = {
{0}
};
#endif
#if IMAGE_BL2U
#ifdef IMAGE_BL2U
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
CSS_MAP_DEVICE,
@ -68,7 +68,7 @@ const mmap_region_t plat_arm_mmap[] = {
{0}
};
#endif
#if IMAGE_BL31
#ifdef IMAGE_BL31
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
@ -77,7 +77,7 @@ const mmap_region_t plat_arm_mmap[] = {
{0}
};
#endif
#if IMAGE_BL32
#ifdef IMAGE_BL32
const mmap_region_t plat_arm_mmap[] = {
V2M_MAP_IOFPGA,
CSS_MAP_DEVICE,

10
plat/arm/board/fvp/fvp_common.c
View File

@ -73,7 +73,7 @@ arm_config_t arm_config;
* The flash needs to be mapped as writable in order to erase the FIP's Table of
* Contents in case of unrecoverable error (see plat_error_handler()).
*/
#if IMAGE_BL1
#ifdef IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_FLASH0_RW,
@ -87,7 +87,7 @@ const mmap_region_t plat_arm_mmap[] = {
{0}
};
#endif
#if IMAGE_BL2
#ifdef IMAGE_BL2
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_FLASH0_RW,
@ -103,14 +103,14 @@ const mmap_region_t plat_arm_mmap[] = {
{0}
};
#endif
#if IMAGE_BL2U
#ifdef IMAGE_BL2U
const mmap_region_t plat_arm_mmap[] = {
MAP_DEVICE0,
V2M_MAP_IOFPGA,
{0}
};
#endif
#if IMAGE_BL31
#ifdef IMAGE_BL31
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
@ -119,7 +119,7 @@ const mmap_region_t plat_arm_mmap[] = {
{0}
};
#endif
#if IMAGE_BL32
#ifdef IMAGE_BL32
const mmap_region_t plat_arm_mmap[] = {
#ifdef AARCH32
ARM_MAP_SHARED_RAM,

10
plat/arm/board/juno/include/platform_def.h
View File

@ -82,27 +82,27 @@
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.
*/
#if IMAGE_BL1
#ifdef IMAGE_BL1
# define PLAT_ARM_MMAP_ENTRIES 7
# define MAX_XLAT_TABLES 4
#endif
#if IMAGE_BL2
#ifdef IMAGE_BL2
# define PLAT_ARM_MMAP_ENTRIES 8
# define MAX_XLAT_TABLES 3
#endif
#if IMAGE_BL2U
#ifdef IMAGE_BL2U
# define PLAT_ARM_MMAP_ENTRIES 4
# define MAX_XLAT_TABLES 3
#endif
#if IMAGE_BL31
#ifdef IMAGE_BL31
# define PLAT_ARM_MMAP_ENTRIES 5
# define MAX_XLAT_TABLES 2
#endif
#if IMAGE_BL32
#ifdef IMAGE_BL32
# define PLAT_ARM_MMAP_ENTRIES 4
# define MAX_XLAT_TABLES 3
#endif

3
plat/arm/common/arm_gicv3.c
View File

@ -79,7 +79,8 @@ void plat_arm_gic_driver_init(void)
* can use GIC system registers to manage interrupts and does
* not need GIC interface base addresses to be configured.
*/
#if (AARCH32 && IMAGE_BL32) || (IMAGE_BL31 && !AARCH32)
#if (defined(AARCH32) && defined(IMAGE_BL32)) || \
(defined(IMAGE_BL31) && !defined(AARCH32))
gicv3_driver_init(&arm_gic_data);
#endif
}

4
plat/common/plat_gicv3.c
View File

@ -36,7 +36,7 @@
#include <interrupt_mgmt.h>
#include <platform.h>
#if IMAGE_BL31
#ifdef IMAGE_BL31
/*
* The following platform GIC functions are weakly defined. They
@ -180,7 +180,7 @@ uint32_t plat_interrupt_type_to_line(uint32_t type,
}
}
#endif
#if IMAGE_BL32
#ifdef IMAGE_BL32
#pragma weak plat_ic_get_pending_interrupt_id
#pragma weak plat_ic_acknowledge_interrupt

8
plat/mediatek/mt6795/include/platform_def.h
View File

@ -156,13 +156,13 @@
/* Size of cacheable stacks */
#if DEBUG_XLAT_TABLE
#define PLATFORM_STACK_SIZE 0x800
#elif IMAGE_BL1
#elif defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
#elif IMAGE_BL2
#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
#elif IMAGE_BL31
#elif defined(IMAGE_BL31)
#define PLATFORM_STACK_SIZE 0x800
#elif IMAGE_BL32
#elif defined(IMAGE_BL32)
#define PLATFORM_STACK_SIZE 0x440
#endif

8
plat/mediatek/mt8173/include/platform_def.h
View File

@ -43,13 +43,13 @@
******************************************************************************/
/* Size of cacheable stacks */
#if IMAGE_BL1
#if defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
#elif IMAGE_BL2
#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
#elif IMAGE_BL31
#elif defined(IMAGE_BL31)
#define PLATFORM_STACK_SIZE 0x800
#elif IMAGE_BL32
#elif defined(IMAGE_BL32)
#define PLATFORM_STACK_SIZE 0x440
#endif

2
plat/nvidia/tegra/include/platform_def.h
View File

@ -40,7 +40,7 @@
******************************************************************************/
/* Size of cacheable stacks */
#if IMAGE_BL31
#ifdef IMAGE_BL31
#define PLATFORM_STACK_SIZE 0x400
#endif

6
plat/qemu/qemu_common.c
View File

@ -68,7 +68,7 @@
* This doesn't include TZRAM as the 'mem_layout' argument passed to
* arm_configure_mmu_elx() will give the available subset of that,
*/
#if IMAGE_BL1
#ifdef IMAGE_BL1
static const mmap_region_t plat_qemu_mmap[] = {
MAP_FLASH0,
MAP_SHARED_RAM,
@ -82,7 +82,7 @@ static const mmap_region_t plat_qemu_mmap[] = {
{0}
};
#endif
#if IMAGE_BL2
#ifdef IMAGE_BL2
static const mmap_region_t plat_qemu_mmap[] = {
MAP_FLASH0,
MAP_SHARED_RAM,
@ -98,7 +98,7 @@ static const mmap_region_t plat_qemu_mmap[] = {
{0}
};
#endif
#if IMAGE_BL31
#ifdef IMAGE_BL31
static const mmap_region_t plat_qemu_mmap[] = {
MAP_SHARED_RAM,
MAP_DEVICE0,

2
plat/rockchip/common/rockchip_gicv3.c
View File

@ -82,7 +82,7 @@ void plat_rockchip_gic_driver_init(void)
* can use GIC system registers to manage interrupts and does
* not need GIC interface base addresses to be configured.
*/
#if IMAGE_BL31
#ifdef IMAGE_BL31
gicv3_driver_init(&rockchip_gic_data);
#endif
}

8
plat/rockchip/rk3368/include/platform_def.h
View File

@ -50,13 +50,13 @@
/* Size of cacheable stacks */
#if DEBUG_XLAT_TABLE
#define PLATFORM_STACK_SIZE 0x800
#elif IMAGE_BL1
#elif defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
#elif IMAGE_BL2
#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
#elif IMAGE_BL31
#elif defined(IMAGE_BL31)
#define PLATFORM_STACK_SIZE 0x800
#elif IMAGE_BL32
#elif defined(IMAGE_BL32)
#define PLATFORM_STACK_SIZE 0x440
#endif

8
plat/rockchip/rk3399/include/platform_def.h
View File

@ -50,13 +50,13 @@
/* Size of cacheable stacks */
#if DEBUG_XLAT_TABLE
#define PLATFORM_STACK_SIZE 0x800
#elif IMAGE_BL1
#elif defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
#elif IMAGE_BL2
#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
#elif IMAGE_BL31
#elif defined(IMAGE_BL31)
#define PLATFORM_STACK_SIZE 0x800
#elif IMAGE_BL32
#elif defined(IMAGE_BL32)
#define PLATFORM_STACK_SIZE 0x440
#endif