From 4af53977533bee7b5763d3efad1448545c2ebef7 Mon Sep 17 00:00:00 2001 From: Manoj Kumar Date: Sun, 10 Jan 2021 16:12:24 +0000 Subject: [PATCH] feat(morello): add changes to enable TBBR boot This patch adds all SOC and FVP related changes required to boot a standard TBBR style boot on Morello. Signed-off-by: sahil Change-Id: Ib8f7f326790b13082cbe8db21a980e048e3db88c --- .../board/morello/fdts/morello_fw_config.dts | 20 ++++ .../morello/fdts/morello_tb_fw_config.dts | 27 +++++ plat/arm/board/morello/include/platform_def.h | 104 +++++++++++++++++- plat/arm/board/morello/morello_bl1_setup.c | 19 ++++ plat/arm/board/morello/morello_bl2_setup.c | 27 +++++ plat/arm/board/morello/morello_bl31_setup.c | 49 +-------- plat/arm/board/morello/morello_def.h | 5 - plat/arm/board/morello/morello_err.c | 17 +++ plat/arm/board/morello/morello_plat.c | 38 ++++++- plat/arm/board/morello/morello_trusted_boot.c | 54 +++++++++ plat/arm/board/morello/platform.mk | 38 +++++-- 11 files changed, 334 insertions(+), 64 deletions(-) create mode 100644 plat/arm/board/morello/fdts/morello_fw_config.dts create mode 100644 plat/arm/board/morello/fdts/morello_tb_fw_config.dts create mode 100644 plat/arm/board/morello/morello_bl1_setup.c create mode 100644 plat/arm/board/morello/morello_bl2_setup.c create mode 100644 plat/arm/board/morello/morello_err.c create mode 100644 plat/arm/board/morello/morello_trusted_boot.c diff --git a/plat/arm/board/morello/fdts/morello_fw_config.dts b/plat/arm/board/morello/fdts/morello_fw_config.dts new file mode 100644 index 000000000..6d48b90f1 --- /dev/null +++ b/plat/arm/board/morello/fdts/morello_fw_config.dts @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/dts-v1/; +/ { + dtb-registry { + compatible = "fconf,dyn_cfg-dtb_registry"; + + tb_fw-config { + load-address = <0x0 0x4001300>; + max-size = <0x200>; + id = ; + }; + }; +}; diff --git a/plat/arm/board/morello/fdts/morello_tb_fw_config.dts b/plat/arm/board/morello/fdts/morello_tb_fw_config.dts new file mode 100644 index 000000000..305a818b0 --- /dev/null +++ b/plat/arm/board/morello/fdts/morello_tb_fw_config.dts @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; +/ { + tb_fw-config { + compatible = "arm,tb_fw"; + + /* Disable authentication for development */ + disable_auth = <0x0>; + + /* + * The following two entries are placeholders for Mbed TLS + * heap information. The default values don't matter since + * they will be overwritten by BL1. + * In case of having shared Mbed TLS heap between BL1 and BL2, + * BL1 will populate these two properties with the respective + * info about the shared heap. This info will be available for + * BL2 in order to locate and re-use the heap. + */ + mbedtls_heap_addr = <0x0 0x0>; + mbedtls_heap_size = <0x0>; + }; +}; diff --git a/plat/arm/board/morello/include/platform_def.h b/plat/arm/board/morello/include/platform_def.h index 9ca75ffe7..6b44cf3b2 100644 --- a/plat/arm/board/morello/include/platform_def.h +++ b/plat/arm/board/morello/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,6 +24,30 @@ #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) +#define MAX_IO_DEVICES U(3) +#define MAX_IO_HANDLES U(4) + +#define PLAT_ARM_FLASH_IMAGE_BASE ULL(0x1A000000) +#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE ULL(0x01000000) + +#define PLAT_ARM_NVM_BASE ULL(0x1A000000) +#define PLAT_ARM_NVM_SIZE ULL(0x01000000) + +#if defined NS_BL1U_BASE +#undef NS_BL1U_BASE +#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000)) +#endif + +/* + * There are no non-volatile counters in morello, these macros points + * to unused addresses. + */ +#define SOC_TRUSTED_NVCTR_BASE ULL(0x7FE70000) +#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + U(0x0000)) +#define TFW_NVCTR_SIZE U(4) +#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + U(0x0004)) +#define NTFW_CTR_SIZE U(4) + /* * To access the complete DDR memory along with remote chip's DDR memory, * which is at 4 TB offset, physical and virtual address space limits are @@ -39,7 +63,36 @@ #endif #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000) -#define PLAT_ARM_MAX_BL31_SIZE UL(0x20000) + +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) + +/* + * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page + */ + +#if USE_ROMLIB +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xE000) +#else +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0) +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0) +#endif + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a + * little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) +#else +# define PLAT_ARM_MAX_BL2_SIZE UL(0x14000) +#endif + +#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) /******************************************************************************* * MORELLO topology related constants @@ -62,12 +115,49 @@ * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the * plat_arm_mmap array defined for each BL stage. */ -#define PLAT_ARM_MMAP_ENTRIES U(9) -#define MAX_XLAT_TABLES U(10) +#if IMAGE_BL1 || IMAGE_BL31 +# define PLAT_ARM_MMAP_ENTRIES U(6) +# define MAX_XLAT_TABLES U(7) +#else +# define PLAT_ARM_MMAP_ENTRIES U(5) +# define MAX_XLAT_TABLES U(6) +#endif -#define PLATFORM_STACK_SIZE U(0x400) +/* + * Size of cacheable stacks + */ +#if defined(IMAGE_BL1) +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE UL(0x1000) +# else +# define PLATFORM_STACK_SIZE UL(0x440) +# endif +#elif defined(IMAGE_BL2) +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE UL(0x1000) +# else +# define PLATFORM_STACK_SIZE UL(0x400) +# endif +#elif defined(IMAGE_BL2U) +# define PLATFORM_STACK_SIZE UL(0x400) +#elif defined(IMAGE_BL31) +# if SPM_MM +# define PLATFORM_STACK_SIZE UL(0x500) +# else +# define PLATFORM_STACK_SIZE UL(0x400) +# endif +#elif defined(IMAGE_BL32) +# define PLATFORM_STACK_SIZE UL(0x440) +#endif #define PLAT_ARM_NSTIMER_FRAME_ID U(0) + +#define PLAT_ARM_TRUSTED_ROM_BASE U(0x0) +#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) /* 128KB */ + +#define PLAT_ARM_NSRAM_BASE ULL(0x06000000) +#define PLAT_ARM_NSRAM_SIZE UL(0x00010000) /* 64KB */ + #define PLAT_CSS_MHU_BASE UL(0x45000000) #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE #define PLAT_MAX_PWR_LVL U(2) @@ -78,6 +168,10 @@ #define MORELLO_DEVICE_BASE ULL(0x08000000) #define MORELLO_DEVICE_SIZE ULL(0x48000000) +/*Secure Watchdog Constants */ +#define SBSA_SECURE_WDOG_BASE UL(0x2A480000) +#define SBSA_SECURE_WDOG_TIMEOUT UL(1000) + #define MORELLO_MAP_DEVICE MAP_REGION_FLAT( \ MORELLO_DEVICE_BASE, \ MORELLO_DEVICE_SIZE, \ diff --git a/plat/arm/board/morello/morello_bl1_setup.c b/plat/arm/board/morello/morello_bl1_setup.c new file mode 100644 index 000000000..915554201 --- /dev/null +++ b/plat/arm/board/morello/morello_bl1_setup.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/******************************************************************************* + * Perform any BL1 specific platform actions. + ******************************************************************************/ + +void soc_css_init_nic400(void) +{ +} + +void soc_css_init_pcie(void) +{ +} diff --git a/plat/arm/board/morello/morello_bl2_setup.c b/plat/arm/board/morello/morello_bl2_setup.c new file mode 100644 index 000000000..0d4b6d00f --- /dev/null +++ b/plat/arm/board/morello/morello_bl2_setup.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include + +void bl2_platform_setup(void) +{ +#ifdef TARGET_PLATFORM_SOC + /* + * Morello platform supports RDIMMs with ECC capability. To use the ECC + * capability, the entire DDR memory space has to be zeroed out before + * enabling the ECC bits in DMC-Bing. + * Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF during BL2 stage, + * as BL33 binary cannot be copied to DDR memory before enabling ECC. + * Rest of the DDR memory space is zeroed out during BL31 stage. + */ + INFO("Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF\n"); + zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); + flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); +#endif + arm_bl2_platform_setup(); +} diff --git a/plat/arm/board/morello/morello_bl31_setup.c b/plat/arm/board/morello/morello_bl31_setup.c index 05a6f4b9b..5a1abe729 100644 --- a/plat/arm/board/morello/morello_bl31_setup.c +++ b/plat/arm/board/morello/morello_bl31_setup.c @@ -36,16 +36,6 @@ struct morello_plat_info { /* Compile time assertion to ensure the size of structure is 18 bytes */ CASSERT(sizeof(struct morello_plat_info) == MORELLO_SDS_PLATFORM_INFO_SIZE, assert_invalid_plat_info_size); -/* - * BL33 image information structure stored in SDS. - * This structure holds the source & destination addresses and - * the size of the BL33 image which will be loaded by BL31. - */ -struct morello_bl33_info { - uint32_t bl33_src_addr; - uint32_t bl33_dst_addr; - uint32_t bl33_size; -}; static scmi_channel_plat_info_t morello_scmi_plat_info = { .scmi_mbx_mem = MORELLO_SCMI_PAYLOAD_BASE, @@ -72,9 +62,7 @@ const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) * enabling the ECC bits in DMC-Bing. Zeroing out several gigabytes of * memory from SCP is quite time consuming so the following function * is added to zero out the DDR memory from application processor which is - * much faster compared to SCP. BL33 binary cannot be copied to DDR memory - * before enabling ECC so copy_bl33 function is added to copy BL33 binary - * from IOFPGA-DDR3 memory to main DDR4 memory. + * much faster compared to SCP. */ static void dmc_ecc_setup(struct morello_plat_info *plat_info) @@ -90,9 +78,8 @@ static void dmc_ecc_setup(struct morello_plat_info *plat_info) assert(plat_info->local_ddr_size > ARM_DRAM1_SIZE); dram2_size = plat_info->local_ddr_size - ARM_DRAM1_SIZE; - VERBOSE("Zeroing DDR memories\n"); - zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); - flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); + INFO("Zeroing DDR memory range 0x%llx - 0x%llx\n", + ARM_DRAM2_BASE, ARM_DRAM2_BASE + dram2_size); zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); flush_dcache_range(ARM_DRAM2_BASE, dram2_size); @@ -201,28 +188,10 @@ static void dmc_ecc_setup(struct morello_plat_info *plat_info) } #endif -static void copy_bl33(uint32_t src, uint32_t dst, uint32_t size) -{ - unsigned int i; - - INFO("Copying BL33 to DDR memory...\n"); - for (i = 0U; i < size; (i = i + 8U)) - mmio_write_64((dst + i), mmio_read_64(src + i)); - - for (i = 0U; i < size; (i = i + 8U)) { - if (mmio_read_64(src + i) != mmio_read_64(dst + i)) { - ERROR("Copy failed!\n"); - panic(); - } - } - INFO("done\n"); -} - void bl31_platform_setup(void) { int ret; struct morello_plat_info plat_info; - struct morello_bl33_info bl33_info; struct morello_plat_info *copy_dest; ret = sds_init(); @@ -256,18 +225,6 @@ void bl31_platform_setup(void) dmc_ecc_setup(&plat_info); #endif - ret = sds_struct_read(MORELLO_SDS_BL33_INFO_STRUCT_ID, - MORELLO_SDS_BL33_INFO_OFFSET, - &bl33_info, - MORELLO_SDS_BL33_INFO_SIZE, - SDS_ACCESS_MODE_NON_CACHED); - if (ret != SDS_OK) { - ERROR("Error getting BL33 info from SDS. ret:%d\n", ret); - panic(); - } - copy_bl33(bl33_info.bl33_src_addr, - bl33_info.bl33_dst_addr, - bl33_info.bl33_size); /* * Pass platform information to BL33. This method is followed as * currently there is no BL1/BL2 involved in boot flow of MORELLO. diff --git a/plat/arm/board/morello/morello_def.h b/plat/arm/board/morello/morello_def.h index 1be7c006d..1ae69cee2 100644 --- a/plat/arm/board/morello/morello_def.h +++ b/plat/arm/board/morello/morello_def.h @@ -22,11 +22,6 @@ #define MORELLO_MAX_DDR_CAPACITY U(0x1000000000) #define MORELLO_MAX_SLAVE_COUNT U(16) -/* SDS BL33 image information defines */ -#define MORELLO_SDS_BL33_INFO_STRUCT_ID U(9) -#define MORELLO_SDS_BL33_INFO_OFFSET U(0) -#define MORELLO_SDS_BL33_INFO_SIZE U(12) - #define MORELLO_SCC_SERVER_MODE U(0) #define MORELLO_SCC_CLIENT_MODE_MASK U(1) #define MORELLO_SCC_C1_TAG_CACHE_EN_MASK U(4) diff --git a/plat/arm/board/morello/morello_err.c b/plat/arm/board/morello/morello_err.c new file mode 100644 index 000000000..4d20a095c --- /dev/null +++ b/plat/arm/board/morello/morello_err.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +/* + * morello error handler + */ +void __dead2 plat_arm_error_handler(int err) +{ + while (true) { + wfi(); + } +} diff --git a/plat/arm/board/morello/morello_plat.c b/plat/arm/board/morello/morello_plat.c index 36bb9e52d..42e5171ca 100644 --- a/plat/arm/board/morello/morello_plat.c +++ b/plat/arm/board/morello/morello_plat.c @@ -4,6 +4,9 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include + +#include #include #include "morello_def.h" @@ -12,7 +15,7 @@ * Table of regions to map using the MMU. * Replace or extend the below regions as required */ - +#if IMAGE_BL1 || IMAGE_BL31 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, MORELLO_MAP_DEVICE, @@ -21,3 +24,36 @@ const mmap_region_t plat_arm_mmap[] = { ARM_MAP_DRAM2, {0} }; +#endif +#if IMAGE_BL2 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + MORELLO_MAP_DEVICE, + MORELLO_MAP_NS_SRAM, + ARM_MAP_DRAM1, +#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3 + ARM_MAP_BL1_RW, +#endif + {0} +}; +#endif + +#if TRUSTED_BOARD_BOOT +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + assert(heap_addr != NULL); + assert(heap_size != NULL); + + return arm_get_mbedtls_heap(heap_addr, heap_size); +} +#endif + +void plat_arm_secure_wdt_start(void) +{ + sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT); +} + +void plat_arm_secure_wdt_stop(void) +{ + sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE); +} diff --git a/plat/arm/board/morello/morello_trusted_boot.c b/plat/arm/board/morello/morello_trusted_boot.c new file mode 100644 index 000000000..f9bc00958 --- /dev/null +++ b/plat/arm/board/morello/morello_trusted_boot.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +/* + * Return the non-volatile counter value stored in the platform. The cookie + * will contain the OID of the counter in the certificate. + * + * Return: 0 = success, Otherwise = error + */ +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + *nv_ctr = MORELLO_FW_NVCTR_VAL; + + return 0; +} + +/* + * Store a new non-volatile counter value. By default on ARM development + * platforms, the non-volatile counters are RO and cannot be modified. We expect + * the values in the certificates to always match the RO values so that this + * function is never called. + * + * Return: 0 = success, Otherwise = error + */ +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + return 1; +} + +/* + * Return the ROTPK hash in the following ASN.1 structure in DER format: + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + */ +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + return arm_get_rotpk_info(cookie, key_ptr, key_len, flags); +} diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk index e09405c7c..b501381fc 100644 --- a/plat/arm/board/morello/platform.mk +++ b/plat/arm/board/morello/platform.mk @@ -30,6 +30,19 @@ MORELLO_GIC_SOURCES := ${GICV3_SOURCES} \ PLAT_BL_COMMON_SOURCES := ${MORELLO_BASE}/morello_plat.c \ ${MORELLO_BASE}/aarch64/morello_helper.S +BL1_SOURCES := ${MORELLO_CPU_SOURCES} \ + ${INTERCONNECT_SOURCES} \ + ${MORELLO_BASE}/morello_err.c \ + ${MORELLO_BASE}/morello_trusted_boot.c \ + ${MORELLO_BASE}/morello_bl1_setup.c \ + drivers/arm/sbsa/sbsa.c + +BL2_SOURCES := ${MORELLO_BASE}/morello_security.c \ + ${MORELLO_BASE}/morello_err.c \ + ${MORELLO_BASE}/morello_trusted_boot.c \ + lib/utils/mem_region.c \ + ${MORELLO_BASE}/morello_bl2_setup.c + BL31_SOURCES := ${MORELLO_CPU_SOURCES} \ ${INTERCONNECT_SOURCES} \ ${MORELLO_GIC_SOURCES} \ @@ -38,19 +51,27 @@ BL31_SOURCES := ${MORELLO_CPU_SOURCES} \ ${MORELLO_BASE}/morello_security.c \ drivers/arm/css/sds/sds.c -FDT_SOURCES += fdts/morello-${TARGET_PLATFORM}.dts +FDT_SOURCES += fdts/morello-${TARGET_PLATFORM}.dts \ + ${MORELLO_BASE}/fdts/morello_fw_config.dts \ + ${MORELLO_BASE}/fdts/morello_tb_fw_config.dts \ + +FW_CONFIG := ${BUILD_PLAT}/fdts/morello_fw_config.dtb +TB_FW_CONFIG := ${BUILD_PLAT}/fdts/morello_tb_fw_config.dtb + +# Add the FW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) +# Add the TB_FW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) + +MORELLO_FW_NVCTR_VAL := 0 +TFW_NVCTR_VAL := ${MORELLO_FW_NVCTR_VAL} +NTFW_NVCTR_VAL := ${MORELLO_FW_NVCTR_VAL} # TF-A not required to load the SCP Images override CSS_LOAD_SCP_IMAGES := 0 -# BL1/BL2 Image not a part of the capsule Image for morello -override NEED_BL1 := no -override NEED_BL2 := no override NEED_BL2U := no -#TF-A for morello starts from BL31 -override RESET_TO_BL31 := 1 - # 32 bit mode not supported override CTX_INCLUDE_AARCH32_REGS := 0 @@ -70,6 +91,9 @@ USE_COHERENT_MEM := 0 # Add TARGET_PLATFORM to differentiate between Morello FVP and Morello SoC platform $(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM}))) +# Add MORELLO_FW_NVCTR_VAL +$(eval $(call add_define,MORELLO_FW_NVCTR_VAL)) + include plat/arm/common/arm_common.mk include plat/arm/css/common/css_common.mk include plat/arm/board/common/board_common.mk